Bottom-Up Performance Analysis of HW/SW Platforms

Richter, Kai; Ziegenbein, Dirk; Jersak, Marek; Ernst, Rolf

doi:10.1007/978-0-387-35599-3_18

Cited by 9 publications

(7 citation statements)

References 19 publications

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“…Following a similar approach, Richter et al operate on workload models [196] to allow the symbolic calculation of execution characteristics. Furthermore, this approach has led to the SymTA/S approach [197] that has been integrated into a commercial product from Symtavision.…”

Section: Analytical Approachesmentioning

confidence: 99%

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Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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Section: Analytical Approachesmentioning

confidence: 99%

“…The SymTA/S approach [197] operates on workload models [196] to allow the symbolic calculation of the execution characteristic. This approach is similar to the above-introduced real-time calculus.…”

Section: Analytical Approachesmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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“…For certain application domains dedicated calculi, task, and workload models exist which allow symbolic evaluation of a design. Richter et al [99] (and the references therein) give an overview of mature analytical techniques for evaluating the task execution on shared resources for event streams, such as periodic events, periodic with jitter, and sporadic preemptions. They extend these techniques by coupling the analytical models using event model interfaces, thus enabling system-level evaluations of platform-based designs.…”

Section: Purely Analytical Approachesmentioning

confidence: 99%

“…This straightforward task is listed as a separate point since the identification of design space constraints can form a significant initial step of a DSE run. The identification of corner cases of the design space could be done, for instance, by probing the design space or by worst-case analytical methods, such as the network calculus [66,113] for the network processing domain and event-stream based methods for the real-time embedded domain [99].…”

Section: Pruning the Design Spacementioning

confidence: 99%

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Methods for evaluating and covering the design space during early design development

Gries

2004

Integration, the VLSI Journal

114

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This paper gives an overview of methods used for Design Space Exploration (DSE) at the system-and micro-architecture levels. The DSE problem is considered to be two orthogonal issues: (I) How could a single design point be evaluated, (II) how could the design space be covered during the exploration process? The latter question arises since an exhaustive exploration of the design space by evaluating every possible design point is usually prohibitive due to the sheer size of the design space. We therefore reveal trade-offs linked to the choice of appropriate evaluation and coverage methods. The designer has to balance the following issues: the accuracy of the evaluation, the time it takes to evaluate one design point (including the implementation of the evaluation model), the precision/granularity of the design space coverage, and last but not least the possibilities for automating the exploration process. We also list common representations of the design space and compare current system and micro-architecture level design frameworks. This review thus eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work. It is focused on System-on-a-Chip designs, particularly those used for network processors. These systems are heterogeneous in nature using multiple computation, communication, memory, and peripheral resources.Keywords: Design space exploration, design space pruning, system-level design, micro-architecture design, design frameworks, benchmarking, multi-objective search. NoteWe focus on related work which applies methods in the context of design space exploration. Discussing the theory of optimization methods and the fundamentals of design evaluation is beyond the scope of this survey.

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