Static and Dynamic Performance Limitations for High Speed D/A Converters

Abstract

Although the digital world gains in importance due to the decreasing feature size of the transistors, the analog building blocks remain indispensable. The design of the interface between the two worlds has to comply with the strict requirements of both sides. The presented research focusses on the design of current steering DI A converters in the modem telecommunication systems of tomorrow.An accurate description of both the static and the dynamic behaviour is of the utmost importance when designing a current steering D/A converter with a high performance. A new formula has been derived that accurately describes the INL-yield of a D/A converter as a function of the transistor mismatch behaviour in a given technology. The influence of systematic errors introduced by linear and quadratic gradients has to be minimised by the use of special switching schemes. Based on these elements, two 12 bit and one 14 bit current steering D/A converter have been implemented.Apart from the three well known factors influencing the dynamic behaviour of the DI A converter, a fourth element has been introduced. The frequency dependency of the output impedance has a negative effect on high resolution, high speed current steering DI A converters. Taking this new element into account during the design resulted in the realisation of a 10 bit D/A converter with a Nyquist performance in the entire frequency band for a clock frequency up to 1 GS/s.To determine the optimal segmentation level of a current steering DI A converter, a statistical analysis has been performed. It could be concluded that if the requirement dictated by the transistor mismatch of the unit current sources is fulfilled , both the INL and the DNL error are smaller than 112 LSB regardless of the number of bits implemented in a binary way. A low segmentation level implies a low decoder complexity and as such leads to a small power and area consumption. Based on these findings , a fully binary 10 bit D/A converter has been realised with a small power consumption and a good dynamic performance.The second part of this work is focussed on transistor mismatch. An overview is given of the most important mismatch models and on the influence of both the immediate surroundings and the used transistor topology. Also the link between the static performance of a current steering D/A converter and the extraction of the transistor vi mismatch parameters has been investigated. It is suggested that a current steering D/A converter could act as a test structure for matching characterisation.

Functionals of Brownian Bridges Arising in the Current Mismatch in D/a Converters

“…Implications of the results derived in this article for the field of DACs can be found in a second article [15]. A comparison with the results in [4,5,11] is summarized in [15, Table 1].…”

“…Furthermore, the advantages of some redundancy-based approaches relying on the DAC statistical INL properties cannot be theoretically estimated; see, for example, [16]. Finally, up to now the main DAC architectures (i.e., binary, thermometer, and segmented) cannot be distinguished with respect to their static linearity properties, so they are wrongly considered identical [2,4]. One conclusion from our results is that the INL for binary and thermometer architectures are different.…”

“…Bastos [2] proposes a much simpler formula, which considers only the deviation of the transfer characteristic at the mid-scale DAC output, which can be a rough, though simple, estimation of the INL max . Another approximation was given by van den Bosch et al [4] by assuming that, if the DAC static transfer characteristic at any code INL has error equal to the target value, e.g., INL k = 0.5 I lsb , then there should be a 50% chance that ultimately INL max is smaller than the target value, i.e., INL k ≤ 0.5 I lsb for all k. The major approximation inaccuracy is in the probability that both the positive and negative INL limits are reached for the same DAC sample, e.g., INL k < −0.5 I lsb is disregarded. Though this approach derives a convenient normal distribution for INL max , it is inaccurate for higher resolutions, as we show in more detail in this paper.…”

Dynamic calibration of current-steering DAC

“…The characterization of DACs' performance can be divided into static and dynamic properties [10] [11]. The static properties are DACs' performance at DC and low frequencies.…”

“…The most common static performances are quantization noise, gain error, offset error, INL, and DNL. The most important static measurements are INL and DNL [10].…”