A compact model for the effect of parasitic internal fringe capacitance on threshold voltage in high-K gate dielectric SOI MOSFETs is developed. Our model includes the effects of the gate dielectric permittivity, spacer oxide permittivity, spacer width, gate length and width of MOS structure. A simple expression for parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. We demonstrate an increase in surface potential along the channel due to these charges resulting in a decrease in the threshold voltage with increase in gate dielectric permittivity. The accuracy of the results obtained using our analytical model is verified using 2-D device simulations.
In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel eld effect transistors (DL-DG-TFETs) with Si 0.5 Ge 0.5 and Si as source material. The CP methodology resolves the issues of random doping uctuation and doping activation. The analog and RF performance has been investigated for both the proposed devices i.e. Si 0.5 Ge 0.5 source DL-DG-TFET and Si-source DL-DG-TFET in terms of drive current, transconductance, cut-off frequency. In addition, the linearity and distortion analysis has been carried out for both the proposed devices with respect to higher order transconductance (g m2 and g m3 ), VIP2, IMD3, and HD2. The Si 0.5 Ge 0.5 source DL-DG-TFET has better performance characteristics and reliability in compare to Si-source DL-DG-TFET owing to low energy bandgap material and higher mobility. The switching ratio obtained for Si 0.5 Ge 0.5 source DL-DG-TFET is order of 5×10 14 that makes it a suitable contender for low power applications.
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