Stateful Logic Operations in One-Transistor-One- Resistor Resistive Random Access Memory Array

Shen, Wensheng; Huang, Peng; Fan, Mengqi; Han, Runze; Zhou, Zheng; Gao, Bin; Wu, Huaqiang; Qian, He; Liu, Lifeng; Liu, Xiaoyan; Zhang, Xing; Kang, Jinfeng

doi:10.1109/led.2019.2931947

Cited by 45 publications

(30 citation statements)

References 25 publications

(17 reference statements)

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“…It must be noted that even the NOR logic primitive is implemented with modifications to the peripheral circuitry of the conventional memory array, namely the row decoder (modified to bias the rows at 'isolation voltage' to prevent unintended NOR operation in those rows) and the WRITE circuitry (modified to apply the MAGIC execution voltage which is twice the WRITE voltage). Similarly, in the NAND-based logic family reported in [37], XOR gate is implemented as a sequence of four NAND operations. This implies that if the fundamental logic primitive of a memristive logic family is weak, all in-memory computation performed using that logic family will be in-efficient (requiring long sequences of operations).…”

Section: Memristive Logicmentioning

confidence: 99%

“…As already stated, a memristive logic family cannot implement such a heterogeneity of gates. As illustrated in Figure 6, the XOR gate has to be implemented as NAND gates [37,49], increasing the logic levels to 12. Such an eight-bit PP adder (Sklansky) is expressed in OR/AND logic primitive and implemented in the memory array in 37 cycles [57].…”

Section: In-memory Eight-bit Adders Using Different Logic Primitivesmentioning

confidence: 99%

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Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Section: Memristive Logicmentioning

confidence: 99%

Section: In-memory Eight-bit Adders Using Different Logic Primitivesmentioning

confidence: 99%

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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“…[10][11][12][13] Recent studies have identified various useful and efficient stateful gates for better computing efficiency, and as a result, stateful logic technology has advanced significantly. [14][15][16][17][18][19][20][21][22][23][24] Such various gates are possible by simultaneously applying designed operating voltages on the multiple cells. In general, the word lines of input cells and output cells are biased to a conditioning voltage (V COND ) and programming voltages (V PGM ), respectively.…”

Section: Introductionmentioning

confidence: 99%

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Kim

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic allows complete in‐memory computing and is considered to be a next‐generation computing technology for low power edge applications. Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near‐memory error correction method for a typical bipolar‐type memristor stateful logic system is proposed. An error correction principles using a HfO2‐based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one‐bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.

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“…In this regard, the bottom panel in Figure a is more realistic. The θ is distributed and the output is a problematic function of the degree of θ variation . Then, for guaranteed gate operation, v i should be higher than the maximum amplitude of θ variation.…”

mentioning

confidence: 99%

“…In this case, the effective array size can be ( n × m ), where m is the number of selected gate lines. This configuration is useful for executing some logic gates in parallel …”

mentioning

confidence: 99%

Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array

Kim

Son

Song

et al. 2020

Advanced Intelligent Systems

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Memristive stateful logic enables energy‐ and cost‐efficient in‐memory computing, which is desirable for edge computing in the coming Internet of Things (IoT) era. Researchers have recently developed various stateful logic gates and have shown viable computing applications based on ideal memristive characteristics. However, few studies have demonstrated a system‐level in‐memory computing operation that can address the practical issues affecting device realization. Herein, a practically viable stateful logic device based on a 1‐transistor−1‐memristor (1T1M) array structure is proposed, considering the inherently stochastic memristor characteristics. Details on how to select the viable stateful logic gates in a given memristor are shown, and as an example of logic cascading, they are implemented in a device to operate a multibit carry look‐ahead adder. Then, an in‐memory computing layout that can perform all of the computing functions—data storing, transferring, and executing—inside the memory, addressing data traffic issues, is suggested. Finally, a software/hardware mixed stateful logic emulator that can virtually mimic array‐level in‐memory computing hardware based on cell‐level memristive characteristics is demonstrated.

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Stateful Logic Operations in One-Transistor-One- Resistor Resistive Random Access Memory Array

Cited by 45 publications

References 25 publications

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array

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Stateful Logic Operations in One-Transistor-One- Resistor Resistive Random Access Memory Array

Cited by 45 publications

References 25 publications

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near‐Memory Computing

Stateful In‐Memory Logic System and Its Practical Implementation in a TaOx‐Based Bipolar‐Type Memristive Crossbar Array

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Resources

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Stateful In‐Memory Logic System and Its Practical Implementation in a TaO_x‐Based Bipolar‐Type Memristive Crossbar Array