Standby power optimization via transistor sizing and dual threshold voltage assignment

Ketkar, Mahesh; Sapatnekar, Sachin S.

doi:10.1145/774572.774628

Cited by 51 publications

(24 citation statements)

References 9 publications

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“…Finally, we compare our results with the results reported by [13] and [18] in the seven common large benchmark circuits that are C880, C1355, C1908, C6288, C7552, i6 and i7. Because the standard cells with different leakage currents are used in [13], [18] and our Leakage Current Solver, we only compare the average reduction percentage of the leakage current rather than the average reduced leakage current.…”

Section: Methodsmentioning

confidence: 73%

“…If the function of pin-reordering in ALGORITHM 1 is turned on, the total leakage current of all circuits constructed by our algorithm is less than the total ESP's minimum and maximum leakage currents by 7% and 24%, respectively. This result is shown in [18] was implemented as a basis of comparison to our algorithm for 12 large benchmark circuits. For each benchmark circuit, RSP randomly generates large number of control-point vectors and records the leakage current data associated with these control-point vectors.…”

Section: Methodsmentioning

confidence: 94%

“…Because the standard cells with different leakage currents are used in [13], [18] and our Leakage Current Solver, we only compare the average reduction percentage of the leakage current rather than the average reduced leakage current. Table V shows the comparison result.…”

Section: Methodsmentioning

confidence: 99%

“…D. Lee et al [16][17] and K. Chopra et al [19] used a branch-and-bound approach and implicit pseudo Boolean enumeration algorithms, respectively, to find a better input vector for reducing the leakage current of a circuit. For solving MLV problem, R. M. Rao et al [18] proposed a greedy search that is based on the controllability of nodes in a circuit and uses the functional dependencies among cells in the circuit to guide the search.…”

Section: Introductionmentioning

confidence: 99%

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A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

Tzeng

Chen

2007

2007 Asia and South Pacific Design Automation Conference

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Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.

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Section: Methodsmentioning

confidence: 73%

Section: Methodsmentioning

confidence: 94%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

Tzeng

Chen

2007

2007 Asia and South Pacific Design Automation Conference

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“…This approach may have significant discretization errors. The third category of works employ combinatorial algorithms [6], [7], which would enumerate and propagate all possible cases while discarding impossible ones with certain pruning criteria. They are normally able to achieve optimal results at the very expensive cost of runtime.…”

Section: Introductionmentioning

confidence: 99%

Improving dual V<inf>t</inf> technology by simultaneous gate sizing and mechanical stress optimization

Lin

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Process-induced mechanical stress is used to enhance carrier mobility and drive current in contemporary CMOS technologies. Stressed cells have reduced delay but larger leakage consumption. Its efficient power/delay trading ratio makes mechanical stress an enticing alternative to other power optimization techniques. This paper proposes an effective urgentpath guided approach that improves dual Vt technique by incorporating gate sizing and mechanical stress simultaneously. The introduction of mechanical stress is shown to achieve 9.8% leakage and 2.8% total power savings over combined gate sizing and dual Vt approach. I. INTRODUCTIONDual V t technique is promising in reducing leakage power consumption. It is based on the fact that high V t cells are less leaky compared to low V t cells. However, high V t cells have longer delay and thus this technique can only be applied to off-critical path and will not be effective when the circuit has a tight timing constraint. In this paper, we propose to explore performance enhancing techniques, gate sizing and mechanical stress used as examples, to improve dual V t technology for further leakage reduction. The key idea is to apply gate sizing and mechanical stress to create delay slacks such that we will be able to assign high V t to cells that would otherwise be assigned low V t due to the timing constraint.Gate sizing technique and dual V t have been commonly leveraged during physical synthesis stage as a tuning strategy for timing closure and power minimization. The problem is known to be a Mixed-Integer Non-Linear Program due to the discrete V t levels and gate sizes, which is of high complexity. One category of works employ sensitivity-based heuristics to guide the selection of gates to be changed, which can be computationally efficient, but far from optimal because of its greedy nature [1], [2]. Another category of works first approximate the discrete problem into continuous formulations, solve the continuous formulation using either optimization techniques like Lagrangian Relaxation [3], [4] or heuristics [5], and then snap the results. This approach may have significant discretization errors. The third category of works employ combinatorial algorithms [6], [7], which would enumerate and propagate all possible cases while discarding impossible ones with certain pruning criteria. They are normally able to achieve optimal results at the very expensive cost of runtime.Today's design has high power efficient requirement and tight timing budget, which makes it challenging to apply dual

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Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment

Lee

Zhai

Blaauw

et al.

Ultra Low-Power Electronics and Design

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Standby power optimization via transistor sizing and dual threshold voltage assignment

Cited by 51 publications

References 9 publications

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

Improving dual V<inf>t</inf> technology by simultaneous gate sizing and mechanical stress optimization

Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment

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