Improving dual V<inf>t</inf> technology by simultaneous gate sizing and mechanical stress optimization

Abstract

Process-induced mechanical stress is used to enhance carrier mobility and drive current in contemporary CMOS technologies. Stressed cells have reduced delay but larger leakage consumption. Its efficient power/delay trading ratio makes mechanical stress an enticing alternative to other power optimization techniques. This paper proposes an effective urgentpath guided approach that improves dual Vt technique by incorporating gate sizing and mechanical stress simultaneously. The introduction of mechanical stress is shown to achieve 9.8% leakage and 2.8% total power savings over combined gate sizing and dual Vt approach. I. INTRODUCTIONDual V t technique is promising in reducing leakage power consumption. It is based on the fact that high V t cells are less leaky compared to low V t cells. However, high V t cells have longer delay and thus this technique can only be applied to off-critical path and will not be effective when the circuit has a tight timing constraint. In this paper, we propose to explore performance enhancing techniques, gate sizing and mechanical stress used as examples, to improve dual V t technology for further leakage reduction. The key idea is to apply gate sizing and mechanical stress to create delay slacks such that we will be able to assign high V t to cells that would otherwise be assigned low V t due to the timing constraint.Gate sizing technique and dual V t have been commonly leveraged during physical synthesis stage as a tuning strategy for timing closure and power minimization. The problem is known to be a Mixed-Integer Non-Linear Program due to the discrete V t levels and gate sizes, which is of high complexity. One category of works employ sensitivity-based heuristics to guide the selection of gates to be changed, which can be computationally efficient, but far from optimal because of its greedy nature [1], [2]. Another category of works first approximate the discrete problem into continuous formulations, solve the continuous formulation using either optimization techniques like Lagrangian Relaxation [3], [4] or heuristics [5], and then snap the results. This approach may have significant discretization errors. The third category of works employ combinatorial algorithms [6], [7], which would enumerate and propagate all possible cases while discarding impossible ones with certain pruning criteria. They are normally able to achieve optimal results at the very expensive cost of runtime.Today's design has high power efficient requirement and tight timing budget, which makes it challenging to apply dual