Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment

Lee, Dongwoo; Zhai, Bin; Blaauw, David; Sylvester, Dennis

doi:10.1007/1-4020-8076-x_4

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…Leakage improvement of 20% with the same gate delay time (compare #4 and #3) was achieved by placing the two H-V t far from the output (T2, T3), as defined by the leakage rule. More details on static leakage reduction through simultaneous V t , T ox and transistors' state assignment can be found in [50]. Table 5.…”

Section: Sleepmentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed

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Section: Sleepmentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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“…The total leakage power of a component having N transistors can be modeled as I sub = I0 · k data · N · fP (σV , T ) · fV (VDD, T ) · fT (T ) (9) where the remainder k data models the state dependency and will be discussed in the following section.…”

Section: Combination Of the Separated Modelsmentioning

confidence: 99%

“…• Leakage-performance tradeoff techniques [9], enabling the choice between fast and low leaking devices. The usefulness of this tradeoff depends on the design.…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Helms

Ehmen

Nebel

2006

Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06

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In this work we present a SPICE-based RTL subthresholdleakage model analyzing components built in 70nm technology [1]. We present a separation approach regarding interand intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude [2,3]. We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed.

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Static Leakage Reduction through Simulteneous VTT/TOX and State Assignment

Cited by 2 publications

References 18 publications

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

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