Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Helms, Domenik; Ehmen, Günter; Nebel, Wolfgang

doi:10.1145/1165573.1165628

Cited by 11 publications

(4 citation statements)

References 28 publications

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“…In the bottom-up model, the DyPa temperature, supply voltage, and body voltage, and the StPa of channel length, oxide thickness, and channel doping are explicit input parameters. In this analytical model [27], only supply voltage, temperature and component state directly enter the model. Bulk voltage, deviating due to ABB indirectly enters the model by modifying the effective threshold voltage.…”

Section: Analytical Rt Top-down Modelmentioning

confidence: 99%

See 1 more Smart Citation

Leakage Models for High-Level Power Estimation

Helms

Eilers

Metzdorf

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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When working in the well established field of register transfer (RT) level modelling, one will soon find out, that doing RT level leakage estimation is by no means a simple modification of timing, area or dynamic power modelling. There are several factors, making leakage macro modelling a unique and completely new challenge: Leakage is barely state dependent from an RT level view. Instead, dynamic parameters highly influencing leakage are temperature ϑ (dominating subthreshold leakage) and supply voltage V DD (having highest influence on gate and pn-junction leakage). Process variations also are a new challenge for RT models. All leakage currents are highly dependent on variation of certain process parameters [1, 2]. Especially the high sensibility to magnitude and distribution of lowest level technological parameters prohibits a simple function-like 'parameters-in estimation-out' model interface. When being used for design space exploration, in-depth information like spread of channel doping concentration may not be available. Instead, RT level leakage models have to integrate parameter distribution prediction and estimation of the resulting leakage currents. Low leakage power management techniques, as adaptive body biasing (ABB) or power gating have large impact on leakage currents. But in contrast to direct leakage reduction techniques as high-k oxides, they have a variable influence on the leakage being controllable from outside an RT component and thus cannot be abstracted within the model. A leakage model supporting leakage power management will thus have to regard these techniques as input parameters. Parameter variation as well as power management techniques will not just affect the leakage current of a component, but also its timing. For a single transistor, the subthreshold leakage, its body potential controlled by ABB, and its operation speed all are highly correlated. Thus a holistic leakage model regarding parameter distribution and power management techniques will have to communicate and share information with an adequate delay model. Only this way, the power-delay correlation, being characteristically for sub-100nm systems and having largest impact on yield, can be described accurately. This thesis will motivate, develop, and evaluate an RT level macro modelling methodology satisfying all these demands. The estimation framework is embedded into the commercial behavioural-to-RT synthesiser tool PowerOpt, where the model predictions guide the synthesis of a SystemC/C++ system specification. The framework consists of the model itself, a floorplan based temperature and voltage drop model, and a variation engine. This engine is translating high level metrics into parameter variation measures, which are then used for leakage and performance prediction. This way, the vii Contents high correlations between leakage and performance [3] as well as the thermo-electrical coupling and electro-electrical coupling [4] which are characteristic for today's devices can be accurately described and thus also automatica...

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Section: Analytical Rt Top-down Modelmentioning

confidence: 99%

“…Best to my knowledge, the only public approaches enabling PTV and state dependent RT level leakage analysis are my empirical bottom-up [26] and my analytical top-down approach [27]. The strengths of the analytical model are easy model characterisation and very fast model evaluation.…”

Section: Analytical Rt Top-down Modelmentioning

confidence: 99%

Leakage Models for High-Level Power Estimation

Helms

Eilers

Metzdorf

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We differentiate between dynamic and static power as well as its source (e. g., functional units, controller, or clock tree). Leakage power at RT-level is nearly independent on data pattern [66] (variation of 15 %) and thus it mainly depends on elapsed time whereas dynamic power depends on the testbench stimuli. In addition the delay is annotated to each basic block which is fixed and can be statically derived from the cycle count within the scheduled CDFG and the frequency.…”

Section: Estimation and Model Generationmentioning

confidence: 99%

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Grüttner

Hartmann

Hylla

et al. 2013

Microprocessors and Microsystems

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The consideration of an embedded device’s power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project

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“…However, in [7] a novel methodology is proposed to estimate distributions of the leakage current of CMOS circuits in presence of process statistical variations integrated with standard BSIM4 and PSP transistor model. The third group consists of statistical leakage estimation based on Look Up Table (LUT) approaches [8][9][10][11]. LUT approach can be further subcategorized in two groups: a first category working at transistor level and second one working at cell level.…”

Section: Introductionmentioning

confidence: 99%