Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bias

Kwai, Ding-Ming

doi:10.1109/asscc.2006.357842

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…To overcome the problem of data storage destruction during the read operation, an 8T cell implementation was used, for which separate write/read bit and word signal lines are used to separate the data retention element and the data output element. Such a cell implementation provides a read-disturb-free operation [6].…”

Section: Figure 2 the Schematic Of 7t Sram Cellmentioning

confidence: 99%

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

Kiran¹,

Saxena²

2016

IJHIT

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Read stability and write ability, or SNM (static noise margin) in total, of a SRAM cell is the effective tool to determine the practicability of the cell. Leakage current, read speed and read stability are few of the constrained parameters desired for any practical SRAM cell. The aim of this paper is to analyze the read behaviour of the multiple SRAM cell structures using cadence tool at 45nm technology and to compare the cells for read operation while keeping the read and write access time and the supply voltage as low as possible. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. A 10T SRAM cell implementation is proposed here that results in reduced leakage power and leakage current, at the same time with increased read stability in comparision with the conventional 6T SRAM cell as well as 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. This paper is aimed to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.

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Section: Figure 2 the Schematic Of 7t Sram Cellmentioning

confidence: 99%

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

Kiran¹,

Saxena²

2016

IJHIT

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“…This calls for the reduction of transistor leakage in an SRAM cell which plays a major role in determining the static power consumption. Most often, the applications stay idle for a relatively long time, and thus, to keep the standby current to the minimum level becomes the main concern [1,2]. There exist more than a few mechanisms that contribute to the leakage, each depending differently on transistor geometry, supply voltage, and ambient temperature [3], [4].…”

Section: Introductionmentioning

confidence: 99%

High Density Low Leakage SRAM Standby Current Reduction with a Channel Stop Implant in p-Type Well in 40nm CMOS Development

Tao

Huang

et al. 2013

ECS Trans.

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In this paper, 32M 0.242 um2 SRAM cell array leakage was reduced significantly by ~ one order of magnitude without affecting the N+/PW junction capacitance after introducing a channel stop implant (CSI) in P-type well. The space for N+ in PW to NW is generally much smaller for SRAM than for logic device, therefore SRAM is normally the weakest point for N+ in PW to NW well isolation. After checking the N+ in PW to NW leakage, we found that its leakage is the dominant factor for the high SRAM standby current. Furthermore, NMOS performance was also improved with this channel stop implant. The N+/PW diode, N+/PW/DNW and P+/NW/PW bipolar were confirmed to be comparable with the baseline without the channel stop implant. P-type well proximity effect (WPE) and NMOS body effect performance were also analyzed.

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Comparison of two SRAM matrix leakage reduction techniques in 45nm technology

Sarfraz

2010

2010 International Conference on Microelectronics

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Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bias

Cited by 6 publications

References 16 publications

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed

High Density Low Leakage SRAM Standby Current Reduction with a Channel Stop Implant in p-Type Well in 40nm CMOS Development

Comparison of two SRAM matrix leakage reduction techniques in 45nm technology

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