Comparison of two SRAM matrix leakage reduction techniques in 45nm technology

Sarfraz, Khawar

doi:10.1109/icm.2010.5696162

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Cited by 3 publications

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“…SRAM operation at such an ultra-low voltage attains low power consumption at the sacrifice of speed performance. Another approach called sleep technology, which scales down supply voltage during data holding as much as memory retention is possible [3], has already been used in SRAM for reducing power consumption. The sleep technology saves power consumption during non-active operations without involving performance penalty for active operations.…”

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confidence: 99%

Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

Uemura

Kato

Matsuyama

et al. 2013

IEEE Trans. Nucl. Sci.

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Abstract-This paper presents soft-error measurement results through neutron and alpha irradiation tests and simulation in SRAM at ultra-low voltages, down to 0.19 V. Soft-error-rate at 0.19 V is higher than at 1.0 V by two orders of magnitude. This measurement result supported by simulation clarifies that direct ionization from secondary protons generated by nuclear reaction with neutron collision contribute to a dramatic increase in SRAM soft-error-rate at ultra-low voltages in terrestrial environment.

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confidence: 99%