Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

Uemura, Tomomasa; Kato, Takashi; Matsuyama, Hideya; Hashimoto, Masanori

doi:10.1109/tns.2013.2291274

Cited by 17 publications

(8 citation statements)

References 21 publications

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“…8-bit MCU was induced by neutron at 0.3V, which suggests large-scale and/or reliability-demanding ultra low-voltage circuits need MCU mitigation techniques. While protons are not dominant secondary particles at 0.4V in this SRAM, a clear observation that secondary protons are causing SEUs will be presented soon [15], and designers must pay attention to drastic SER increase. Near-threshold computing at 11nm, which is drawing attention in exa-scale computing, is likely to face with this secondary proton problem.…”

Section: Discussionmentioning

confidence: 98%

“…Therefore, He and heavier ions are the dominant secondary ions causing SEUs in 0.4-V operation because these ions occupy 89 % of the SEU probability at 1.4 fC of critical charge. At 0.4V operation, protons are not dominant, but an upcoming result with other SRAM at 0.19V will present a dramatic SEU increase, which is well explained by proton contribution [15].…”

Section: Simulationmentioning

confidence: 91%

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Soft error immunity of subthreshold SRAM

Hashimoto

2013

2013 IEEE 10th International Conference on ASIC

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Abstract-This paper discusses soft error immunity of subthreshold SRAM presenting neutron-and alpha-induced soft error rates (SER) in 65-nm 10T SRAM over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is 7.8 times as high as that at 1.0 V. The measured multiple cell upsets (MCUs) included 8-bit MCU. With 0.4V operation of the SRAM under test, protons are not dominant secondary particles causing SEU, but this paper points out that protons must be considered for future near-threshold computing. The alpha-induced SER at 0.3V is 6x higher than that at 1.0V. These results can contribute to reliability estimation and enhancement in subthreshold circuit design.

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Section: Discussionmentioning

confidence: 98%

Section: Simulationmentioning

confidence: 91%

Soft error immunity of subthreshold SRAM

Hashimoto

2013

2013 IEEE 10th International Conference on ASIC

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“…In this section, we discuss the effects of SCT on proposed SDS‐FinFET [7]. Our investigations focus on the change in the

I_{D}

induced by the trapping of an individual electron in an acceptor type interface state at the Si/SiO 2 interface in n‐FinFET.…”

Section: Single Charge Trapping Analysismentioning

confidence: 99%

“…These high energy particles may trap into the semiconductor devices through the IC package and make a circuit unstable. Major reliability issues come when these particles trap into the silicon-insulator interface [7]. This analysis is disused by Fan et al [8] for the single gate and individual (double) gate-based FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Yadav

Shah

Beohar

et al. 2019

Micro & Nano Letters

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High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

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“…The importance of considering energy deposition straggling when calculating SEU rates in advanced SRAMs may be illustrated by work recently published by Uemura et al [40]. Uemura used the Particle and Heavy Ion Code System (PHITS) version 2.52 [41] to demonstrate the role of direct ionization by secondary protons (protons produced by a neutron nuclear reaction) as the dominant mechanism in terrestrial environments for SEU in highly scaled SRAMs at reduced bias.…”

Section: Effect Of Energy Loss Straggling In Small Volumesmentioning

confidence: 99%

Limitations of LET in Predicting the Radiation Response of Advanced Devices

Funkhouser

Weller

Reed

et al. 2015

IEEE Trans. Nucl. Sci.

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The impact of high-Z metals on energy deposition in thin volumes due to direct ionization by ions in space environments is examined. The importance of energy loss straggling in small volumes typical of those found in advanced devices is also evaluated. It is found that direct ionization by protons over a large energy range may contribute significantly to error rates in advanced silicon on insulator devices due to energy loss straggling. This improves on conventional event rate analysis based on linear energy transfer, which does not describe the contributions of direct ionization by protons to the error rate.

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Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment

Cited by 17 publications

References 21 publications

Soft error immunity of subthreshold SRAM

Soft error immunity of subthreshold SRAM

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

Limitations of LET in Predicting the Radiation Response of Advanced Devices

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