STAHL: A Novel Scan-Test-Aware Hardened Latch Design

Ma, Ruijun; Holst, Stefan; Wen, Xiaoqing; Yan, Aibin; Xu, Haiwen

doi:10.1109/ets.2019.8791544

Cited by 7 publications

(2 citation statements)

References 18 publications

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“…Because each CRP can only be used once, and the CRP-list on a server shrinks over time [7]. • The scan chain: Note that DFT techniques are widely used in contemporary ICs [32]. All-Spin PUF reuses the scan chain to implement its functionality.…”

Section: The Structure Of All-spin Pufmentioning

confidence: 99%

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Zhang

Ren

et al. 2022

J. Emerg. Technol. Comput. Syst.

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Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-In-Memory (CIM) system. However, it is challenging to guarantee the hardware security of STT-mCell based all spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for STT-mCell based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61 \(\% \) . With \(\pm 20\% \) supply voltage, and 5°C-105°C temperature variations, All-Spin PUF shows a strong resiliency. In comparison with the state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of All-Spin PUF against emerging modeling attack is verified as well.

show abstract

Section: The Structure Of All-spin Pufmentioning

confidence: 99%

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Zhang

Ren

et al. 2022

J. Emerg. Technol. Comput. Syst.

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show abstract

“…The LFSR ensures the diversity of challenges for a 64-bit signature. • The scan chain structure: Note that DFT techniques are widely used in contemporary ICs [32]. SD-PUF reuses the scan chain to implement its functionality.…”

Section: B the Detailed Implementation Of Sd-pufmentioning

confidence: 99%

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

Chen

et al. 2021

IEEE Trans. VLSI Syst.

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An ultra low‐power double‐node‐upsets hardened latch design

Chen,

Xie,

Liang

et al. 2024

Circuit Theory & Apps

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In this paper, a novel low‐cost, double‐node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low‐cost profile. The proposed latch is based on a low‐cost single event double‐node upset tolerant latch and also provides self‐recoverability against double‐node‐upsets. The latch uses clock‐controlled DICE (Dual‐interlocked storage cell) cell and CE(C‐Elements) cell to tolerate double‐node‐upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area‐power‐delay product (APDP) of the proposed low‐power double‐node‐upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature.

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STAHL: A Novel Scan-Test-Aware Hardened Latch Design

Cited by 7 publications

References 18 publications

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

An ultra low‐power double‐node‐upsets hardened latch design

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