All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

Abstract

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-In-Memory (CIM) system. However, it is challenging to guarantee the hardware security of STT-mCell based all spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for STT-mCell based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61 \(\% \) . With \(\pm 20\% \) supply voltage, and 5°C-105°C temperature variations, All-Spin PUF shows a strong resiliency. In comparison with the state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of All-Spin PUF against emerging modeling attack is verified as well.

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“…Therefore, a 2D sequence-dependent SRAM PUF is designed [208] that increases the CRPs is designed. Large amounts of power are consumed by traditional CMOS PUFs, A PUF design for all-spin circuits based on STT-mCell technology a linear feedback shift register (LFSR) with K stages is used [210]. A unique PUF design and generation scheme that uses resistive random access memory (RRAM) cells' inherent program-time variation as an entropy source as CMOS is vulnerable to secure communication [211].As conventional CMOS is also suffering from scaling constraints a high level of reliability was attained by an RRAM PUF based on two transistors two RRAM (2T2R) cells [212].…”