2021
DOI: 10.1109/tvlsi.2021.3073415
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DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

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Cited by 3 publications
(1 citation statement)
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“…To boost processing speed, a sketch's update and query process should be straightforward and ideally only access CPU caches when handling high-speed data streams [19]. CPU cache memory is divided into three levels: L1, L2 and L3, among which the L1 cache is the fastest, but of size restricted to between 8KB and 64KB in general [27,28], forcing sketches to be compact enough. Sketches with small sizes bring benefits in many practical scenarios, e.g., to compress gradients and accelerate the training process in distributed machine learning [29][30][31].…”
Section: Introductionmentioning
confidence: 99%
“…To boost processing speed, a sketch's update and query process should be straightforward and ideally only access CPU caches when handling high-speed data streams [19]. CPU cache memory is divided into three levels: L1, L2 and L3, among which the L1 cache is the fastest, but of size restricted to between 8KB and 64KB in general [27,28], forcing sketches to be compact enough. Sketches with small sizes bring benefits in many practical scenarios, e.g., to compress gradients and accelerate the training process in distributed machine learning [29][30][31].…”
Section: Introductionmentioning
confidence: 99%