Square-rich fixed point polynomial evaluation on FPGAs

Abstract

Polynomial evaluation is important across a wide range of application domains, so significant work has been done on accelerating its computation. The conventional algorithm, referred to as Horner's rule, involves the least number of steps but can lead to increased latency due to serial computation. Parallel evaluation algorithms such as Estrin's method have shorter latency than Horner's rule, but achieve this at the expense of large hardware overhead. This paper presents an efficient polynomial evaluation algorithm, which reforms the evaluation process to include an increased number of squaring steps. By using a squarer design that is more efficient than general multiplication, this can result in polynomial evaluation with a 57.9% latency reduction over Horner's rule and 14.6% over Estrin's method, while consuming less area than Horner's rule, when implemented on a Xilinx Virtex 6 FPGA. When applied in fixed point function evaluation, where precision requirements limit the rounding of operands, it still achieves a 52.4% performance gain compared to Horner's rule with only a 4% area overhead in evaluating 5 th degree polynomials.

Fracturable DSP Block for Multi-context Reconfigurable Architectures

“…We also compare the results of folding level 0, which can be considered equivalent to a single context FPGA, against the results on an Altera Stratix V (5SGSMD4E1H29C1) device that features 6-input fracturable LUTs and variable precision DSPs, as shown in Table 2. To account for the difference in platforms, we compute the effective area utilized by the implementation (in terms of equivalent LUTs) using the relation A Eff = LUT Max /DSP Max * DSPutilization + LUTutilization [13]. Also, the number of multiply/MAC and add/sub operations in each benchmark is shown (in brackets), which helps determine the reduction in DSP blocks achieved by exploiting their fracturable nature (on Stratix V and on the proposed DSP block in NATURE).…”

Mapping for Maximum Performance on FPGA DSP Blocks

“…This requires the datapaths to be manually tailored around the low-level structure of the DSP block, maximizing use of supported features. More general application to polynomial evaluation has also been proposed, again with detailed low-level optimization around DSP block structure [8]. The flexible DSP blocks in Xilinx FPGAs have also been exploited as the main functional unit in a soft processor [9].…”

The iDEA DSP Block-Based Soft Processor for FPGAs

“…DSP blocks are more power efficient, operate at a higher frequency, and consume less area than the equivalent operations implemented using the logic fabric. As such, they are heavily used in the pipelined datapaths of computationally intensive applications [de Dinechin and Pasca 2011;Xu et al 2014]. However, we have found that DSP block inference by the synthesis tools can be suboptimal [Ronak and Fahmy 2012] and the dynamic programmability feature is not mapped except in very restricted cases.…”