The iDEA DSP Block-Based Soft Processor for FPGAs

Abstract

DSP blocks in modern FPGAs can be used for a wide range of arithmetic functions, offering increased performance while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in other application domains they may be underutilised. The DSP48E1 primitives in new Xilinx devices support dynamic programmability that can help extend their usefulness; the specific function of a DSP block can be modified on a cycle-by-cycle basis. However, the standard synthesis flow does not leverage this flexibility in the vast majority of cases. The lean DSP Extension Architecture (iDEA) presented in this article builds around the dynamic programmability of a single DSP48E1 primitive, with minimal additional logic to create a general-purpose processor supporting a full instruction-set architecture. The result is a very compact, fast processor that can execute a full gamut of general machine instructions. We show a number of simple applications compiled using an MIPS compiler and translated to the iDEA instruction set, comparing with a Xilinx MicroBlaze to show estimated performance figures. Being based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, Virtex-7, and Zynq families.

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

“…The interconnect structure is typically connects nearest neighbors (NN), allowing FUs to communicate only with neighboring FUs. The FUs themselves can be simple soft processors, such as the Xilinx Microblaze [29] or iDEA [30]. However, the movement of data and keeping the processors busy with computation presents a complex scheduling problem, resulting in poor performance.…”

“…The presence of hard DSP rich FPGA fabrics in modern devices, and previous work [30] that demonstrated how DSP blocks can be used for general processing at near to their theoretical limits, suggested that DSP blocks should be used as FUs to improve overlay resource usage. A fully pipelined DSP block based throughput oriented overlay architecture [34] was mapped to a Xilinx Zynq XC7Z020 device.…”

Fracturable DSP Block for Multi-context Reconfigurable Architectures

“…DSP48E1 blocks also offer dynamic programmability that allows their function to be altered at run-time using control inputs, allowing them to be used flexibly. An example case is shown in [3], where a DSP48E1 block forms the execution unit of a highly efficient soft-processor. Altera's variable precision DSP block can perform multiple sub-width operations concurrently (up to 3 9 × 9) with a design-time decision, while also featuring extensions like coefficient memory for efficient implementation of filters [1].…”

“…These support different computational precision and re-use of resources. The DSP blocks in Xilinx FPGAs offer dynamic programmability, that allows their function to be altered at run-time using special control inputs, improving their flexibility, as shown in [3] where they are used in the execution unit of a soft-processor. However, the compute precision of these DSP blocks cannot be altered across clock cycles, preventing them from being reused efficiently in a mixed precision circuit implementations, specifically on multi-context architectures that support TLF.…”

Minimizing DSP block usage through multi-pumping

“…This greatly enhances the capabilities of a DSP48E1 primitive, as it can be reprogrammed and multiple different operations can be mapped to a single DSP block. This flexibility has been exploited to create lean soft processors [1] and to support high performance programmable overlays [2].…”