Spurious source/drain underlap of large junction area NFET's

Abstract

When a 0.35-m CMOS technology was introduced into manufacturing, a small fraction of the tested devices exhibited symptoms of source/drain underlap, despite the fact that all other monitors were well within the design control limits. Additional measurements showed variable overlap on various monitor structures on the same chip. The specific formulation of an HF wet clean was shown to be responsible for the underlapped devices, and the problem was eliminated by altering this process step. High-volume manufacturing data are presented to show the problem and the solution.Index Terms-Semiconductor device manufacture, semiconductor device reliability, semiconductor logic devices.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…We use the concept of gate-underlap design which has been studied extensively for digital [12][13][14][15][16][17][18] and analog/rf [19][20][21][22][23] applications. In high-volume manufacturing, gate-source/drain underlap devices were 'accidentally' fabricated in 0.35 micron CMOS technology [24]. Since then, gate-underlap concept has been intentionally applied and experimentally demonstrated for 16 nm bulk MOSFET [25] and 10 nm FinFETs [26] for digital applications and 0.14 lm single gate SOI MOSFETs [27] for rf applications.…”

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

“…In high-volume manufacturing, gate-source/drain underlap devices were 'accidentally' fabricated in 0.35 μm CMOS technology [29]. Since then, gate-underlap concept has been 'intentionally' applied and experimentally demonstrated for 16 nm bulk MOSFET [30], 10 nm FinFETs [31], 50 nm multi-channel MOSFETs [32], 1 T-DRAM cell [33] and URAM cell [34] for digital applications, 0.14 μm single gate SOI MOSFETs [35] for RF applications and 50 nm multibridge channel MOSFETs for analog/RF applications [36].…”