Spurious free time-to-digital conversion in an ADPLL using short dithering sequences

Waheed, K.; Sheba, Mahbuba; Staszewski, Robert Bogdan; Dulger, F.; Vamvakos, Socrates D.

doi:10.1109/cicc.2010.5617430

Cited by 9 publications

(4 citation statements)

References 21 publications

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“…Using and , is derived as (5). The delay time of each TDC buffer varies under PVT environments with the development of time, hence leading to a fluctuation of that results in serious jitter noise under steady state [10], [20]. In order to remove the PVT variation effect, the raw value for must be normalized by through the -normalization block of Fig.…”

Section: A Low-power Tdc Based On Retimed Reference Clocksmentioning

confidence: 99%

“…20 in which the largest spur level is at 470 kHz offset and the closest spur is 230 kHz (470 kHz/2). The sub harmonic and harmonic spurs can be originated from a DCO quantization, a TDC quantization, an intermodulation related to the amount of inherent jitter, and a parasitic coupling of CKR-controlled switching in many digital gates sharing the same substrate, power and ground planes with DCO [5], [8], [20], [21]. The ADPLL phase noise curves measured using Agilent E5052B signal source analyzer are plotted like in Fig.…”

Section: Whenmentioning

confidence: 99%

“…Among those research results [1]- [20], all-digital PLLs (ADPLLs) where all input and output signals are digitalized have been developed to be utilized in RF transmitters for direct frequency/phase modulation. In common ADPLLs, a time-to-digital converter (TDC) that has a significant impact on in-band phase noise as well as power consumption is devised to track and correct the fractional part of the phase error between the two asynchronous input clocks: the low-rate frequency reference (FREF) and high-rate variable oscillator (CKV) clocks.…”

Section: Introductionmentioning

confidence: 99%

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A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Lee

Park

Min

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves in-band phase noise, integrated noise, and 740 ns settling time.

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Section: A Low-power Tdc Based On Retimed Reference Clocksmentioning

confidence: 99%

Section: Whenmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Lee

Park

Min

et al. 2012

IEEE Trans. Circuits Syst. I

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“…To prevent the noise level from increasing due to the input jitter, a Σ∆ modulator is used to shape the noise at the input of the BBPLL. [30] uses a noise shaped short period pattern to randomize a TDC based ADPLL to smooth out the output spectrum. These two techniques are used in the present work to achieve a versatile and portable design that improves the performance of the BBPLL.…”

Section: Spur Reduction In Bang-bang Plls Using a Programmable Bit-stmentioning

confidence: 99%

Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

Amid¹

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ii Abstract The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang phase-locked loop is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined Σ∆ modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.The second part of the research focuses on a novel multi-bit phase detector for high-speed applications where high-resolution performance is needed and the jitter budget is stringent. In this design a Transmission Delay Line is used to generate the delayed versions of the input clock. The performance of this phase detector is analyzed in detail using stochastic analysis.In the second multi-bit phase detector a search algorithm is used to find i the closest delayed reference to the feedback clock. This scheme provides superior performance compared to the first scheme as its performance is not affected by the mismatch of the binary phase detectors used in the first scheme. The performance of the two design are compared and example of the performance in the loop is provided.ii

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