A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Abstract

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves in-band phase noise, integrated noise, and 740 ns settling time.

A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology

“…So the digital power can be reduced to about 6 mW. As a result, the total power of our ADPLL can be lowered to about 10.8 mW, which lies in the same level with other works in [2][3][4][5][6][7].…”

“…In this work, f REF is 13 Fig. 3 Simulated settling process about 2 MHz, so R P is about 6.5 according to (7). Note that the word length of R P is also determined by (7), e.g.…”

“…This indicates that good phase noise performance is Table 1 provides a comparison of this work with other relevant works. First, the 130 cycles settling is the second fastest in all the works in [2,[4][5][6][7]11] only slower than [7]. Second, the 180 nm CMOS process we adopted is the cheapest for fabrication cost.…”

“…Nevertheless, the 40 MHz reference frequency is the same as in [6], so the settling still takes 240 reference cycles; moreover, the design is based on a 65 nm CMOS process. Although the settling time is reduced to 44 reference cycles by a phase-error compensator (PEC) and a loop-settling monitor (LSM) in [7], it requires many combination logics in the PEC and LSM whose delays greatly depend on the size of CMOS process. As a result, [7] implemented the ADPLL with an advanced technology of 90 nm.…”

“…Although the settling time is reduced to 44 reference cycles by a phase-error compensator (PEC) and a loop-settling monitor (LSM) in [7], it requires many combination logics in the PEC and LSM whose delays greatly depend on the size of CMOS process. As a result, [7] implemented the ADPLL with an advanced technology of 90 nm.…”