Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

Waheed, K.; Staszewski, Robert Bogdan; Dulger, F.; Ullah, Mahbuba Sheba; Vamvakos, Socrates D.

doi:10.1109/tcsi.2011.2163981

Cited by 19 publications

(4 citation statements)

References 18 publications

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“…Similar conclusion was reached in Ref. [33], which investigated the adverse effects of near-integer-N PLL operation and dithering as a means to mitigate them. Note that the DTC-TDC pair could be viewed as a complex TDC comprising two stages: coarse (i.e., full-range DTC) and fine (i.e., narrow-range TDC).…”

Section: Phase Prediction Blocksupporting

confidence: 83%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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Section: Phase Prediction Blocksupporting

confidence: 83%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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“…At the same time, the new wireless standards require low in-band PN and spurious tones. While the improved TDC resolution TDC (≡K T DC as defined above) helps to lower the in-band quantization noise, the TDC transfer function non-linearity (i.e., INL) can create fractional spurs especially at close to integer-N channels or at wide PLL loop bandwidths [31]. Consequently, both TDC and INL must improve.…”

Section: Time-to-digital Converter (Tdc)mentioning

confidence: 99%

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Kuo

Babaie

Chen

et al. 2018

IEEE Trans. Circuits Syst. I

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We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2 . Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTIONM OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript

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“…Recently, due to the progress in CMOS technology, the propagation time of inverter, determining the resolution of TC, has reached the level of 15-30 ps. [19][20][21] To achieve a resolution better than 15 ps, some authors try to use state-of-the-art more complex methods of time-to-digital conversion. 4, 7-10, 18, 22-24 A delay line consisting of parallel elements can also be used to overcome this problem.…”

Section: Second Interpolation Stagementioning

confidence: 99%

A 7.5 ps single-shot precision integrated time counter with segmented delay line

Klepacki

Szplet

Pełka

2014

Review of Scientific Instruments

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This paper describes the design and test results of time interval counter featuring the single-shot precision of 7.5 ps root mean square (rms) and measurement range of 1 ms. These parameters have been achieved by combining direct counting method with a two-stage interpolation within a single clock period. Both stages of interpolation are based on the use of tapped delay lines stabilized by delay locked loop mechanism. In the first stage, a coarse resolution is obtained with the aid of high frequency multiphase clock, while in the second stage a sub-gate delay resolution is achieved with the use of differential delay line. To reduce the nonlinearities of conversion and to improve the precision of measurement, a novel segmented delay line is proposed. An important feature of this segmented delay line is partial overlapping of measurement range and resulting enhancement of both resolution and precision of time interval counter. The maximum integral nonlinearity error of the fine-stage interpolators does not exceed 16 ps and 14 ps in START and STOP interpolators, respectively. These errors have been identified by statistical calibration procedure and corrected to achieve single-shot precision better than 7.5 ps (rms). The time counter is integrated in a single ASIC (Application Specific Integrated Circuit) chip using a standard cost-effective 0.35 μm CMOS (Complementary Metal Oxide Semiconductor) process.

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Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

Cited by 19 publications

References 18 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

A 7.5 ps single-shot precision integrated time counter with segmented delay line

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