An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

Abstract

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2 . Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTIONM OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

“…with 6 dB per octave of F CW . The error with the fitting line (19) depends only on L, i.e. on the ratio F CW/GCD 2 N , F CW , as shown in Fig.…”

“…We chose the case N = 6 and N DTC = 5 for plot readability. The worst quantization spur does not depend on the clock frequency itself, but only on the ratio f DDS /f CK , as can be shown by re-writing (19) using (1):…”

“…Moreover, from (19), the worst quantization spur increases by 6 dB every octave increase in F CW . This result can intuitively be understood by realizing that the average frequency is defined by the adder, while the DTC compensates for deterministic jitter, leaving a rather random residual quantization rms-error with power ∆ 2 /12 related to the LSB-delay ∆ of the DTC.…”

“…Therefore, the worst-case spur can be approximated as: Fig. 10a shows the magnitude of the worst-case spur (in dBc) as a function of F CW , from (13) and (14), as well as its approximation (19). We chose the case N = 6 and N DTC = 5 for plot readability.…”

“…Thus, frequency synthesizers are often benchmarked in terms of maximum spur, e.g. fractional-N PLLs [19]- [21].…”