High linearity CMOS radio receivers often exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband. Due to nonlinearity and finite gain in the OpAmp, virtual ground is imperfect, inducing distortion currents. This paper proposes a negative conductance concept to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. In-and out-of-band linearity, stability and Noise Figure are also analyzed. The technique is applied to linearize an RF receiver, and a prototype is implemented in 65 nm technology. Measurement results show an increase of in-band IIP 3 from 9dBm to >20dBm, and IIP2 from 51 to 61dBm, at the cost of increasing the noise figure from 6 to 7.5dB and <10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <27mA up to 2GHz for 1.2V supply voltage.

A single-trim, highly accurate Colpitts-based frequency reference is presented. Our analysis shows that the Colpitts-topology outperforms the cross-coupled LC-topology in terms of temperature stability. Measurements on prototypes in a 0.13 µm high voltage CMOS SOI process were carried out from −50 to 170°C. Based on sample-specific single room temperature trim and batch calibration, our frequency reference achieves an accuracy of ±120 ppm for 16 samples from a single wafer utilized for extracting the batch-calibration polynomial, and ±300 ppm for 48 samples across 3 wafers from the same batch. This is a 4x improvement over related single-trim stateof-the-art solutions. Frequency drift due to ageing, tested after a 6-day 175°C storage, is below 100 ppm. The oscillator core dissipates 3.5 mW from a 2.5 V supply and has 220 ppm/V supply-sensitivity without supply regulation.

This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in today's deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights.The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations.

Abstract:A highly linear Π attenuator system using a wideband IM3 cancellation technique is presented that provides 4 discrete attenuation levels with 6dB spacing for DC-5GHz. For the whole band, S11<-14dB, attenuation flatness<1.6dB, +10dBm input P 1dB and +26dBm IIP3 are achieved. For the TV band (0.1Gz-1.2GHz) +30dBm IIP3 is achieved. The active area is 0.0054mm 2 in a standard 0.16um bulk CMOS process. Text:In the receiver path and in spectrum analyzers typically gain control blocks are used to limit the incident power to the level that the receiver circuitry can handle without degrading the linearity; in the transmitter path stringent power control is also desirable. Although variable-gain amplifiers (VGAs) traditionally implement the gain control block, attenuators based on FET transistors show superior performances on linearity, power handling capability and power consumption. where W is the transistor width. In deriving (1) the transistors' 3rd-order output conductance nonlinearity is assumed to dominantly contribute to IM3. Eq. (1) suggests that in the Π attenuator, the IM3 current of M 1 at least partially cancels the IM3 current of M 2 and M 3 at the there is full IM3 cancellation within the Π attenuator, which is robust since it only relies on the ratio of transistor widths; then IIP3 is limited by mechanisms such as capacitive nonlinearity.To verify the concept of (1) we implemented the Π attenuator shown in Fig. 4 A four-branch attenuator system with selectable attenuation, see Fig. 4.3.3, using this IM3 cancellation technique was fabricated in a standard 0.16um CMOS process. Each branch contains one Π attenuator that uses the topology shown in Fig. 4.3.1 (upper) and is designed for one specific attenuation setting (-6dB, -12dB, -18dB and -24dB) and optimized for full IM3 cancellation (transistor W fixed by (1)). A 3-to-8 digital decoder provides the controlling voltage (1.8V for enabling and 0V for disabling). The active area of the attenuator and the decoder is 50x30 um 2 and 60x65 um 2 respectively. For each of the forenamed attenuation settings, only one branch is enabled. For minimum signal attenuation, the series transistors in all four branches are enabled, and the shunt transistors in all four branches are disabled, yielding an additional -1.8dBattenuation. For isolation and ac-bootstrapping purposes, the gate of transistor M 1 in the Π attenuators is connected to the controlling voltage via a 20kΩ resistor; while the bulk is connected to GND via a 20kΩ resistor. The attenuator (see Fig. 4.3.7) was measured by on-wafer probing. The two-tone spacing is 3.2MHz for all measurements. Due to a mistake in the decoder design, the minimum attenuation setting (-1.8dB) cannot be enabled. For this setting we only show the simulated S11/S21. Due to unaccounted parasitics, the measured S21 for f rf >5GHz deviates >1.6dB from simulation. Since the proposed IM3 cancellation does not require large transistors, 5GHz bandwidth is achieved with S11<-14dB and 5 with S21 variation <1.6 dB. The difference betwee...

Cross-correlation can be used in energy detection applications, such as spectrum analyzers, but also frequency shift keying (FSK) receivers, to improve noise suppression. To achieve higher signal-to-noise ratio (SNR), integration in time may be used, but could make it rather slow for communication purposes. In order to achieve better data-rates in low SNR conditions, we propose to use multiple chains instead of the traditional two chains. In this paper, we show an analysis of the SNR improvement and the power consumption penalty for BFSK modulation when using more chains. It shows that for low noise correlation between the chains, the improvement in sensitivity is proportional to the number of chains. Also, we develop a figureof-merit to evaluate the optimum number of chains for different parameters of the receiver design. Furthermore, two examples from literature are analyzed. At their optimum number of chains, they both show ∼6dB improvement in sensitivity with similar or even better figure-of-merit.

Wireless sensor networks have recently emerged in a wide range of applications. Many attributes are essential for such networks such as: low cost, small form-factor, limited peak power consumption and the ability to operate in harsh interference scenarios. Most of these networks do not require high data-rates to operate. In this respect, sub-sampling receivers have shown promising results but suffer from noise folding and interference aliasing. In this paper, a sub-sampling receiver in combination with cross-correlation is used to enhance sensitivity and interference robustness while maintaining the sub-sampling advantages. An architecture which uses two different sampling frequencies is proposed. It shows ∼2dB SNR improvement compared to traditional architectures due to cross-correlation and an additional ∼2dB for each doubling of integrations. For a BER of 10 −3 , the required SIR is reduced with 4.5dB, 11.5dB and 14.5dB after using cross-correlation with the same, half and quarter data-rate used respectively. These improvements allow for a lower-power and lower-cost implementation.

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A single-trim, high accuracy frequency reference is presented. The Colpitts LC-oscillator topology reduces the temperature dependencies of the LC-tank quality factor on the oscillation frequency. With a fractional divider for frequency compensation it can serve as crystal-replacement. Measurements of the prototype (16 samples) in a 0.13µm high-voltage CMOS SOI process show ±120ppm accuracy from-50 to 170°C. The oscillator dissipates 3.5mW from a 2.5V supply and has 220ppm/V supply-sensitivity without supply regulation.