Split Parallel Semibridge Switching Cells for Full-Power-Range Efficiency Improvement

Abstract

This paper proposes a positively-coupled-inductor (PCI) based paralleling scheme for basic semi-bridge switching cells which are formed by power MOSFETs and diodes. Both the semi-bridge switching cells and the inductors are split into two parallel parts, and thus, a small differential-mode inductance is formed between the midpoints of the parallel semi-bridge switching cells. A time-delay-based modulation strategy is applied to generate a controllable circulating current which enables all active switches to achieve the zero-current switching (ZCS) or zero-voltage switching (ZVS), and all diodes to achieve ZCS turn-off. Accordingly, the switching loss and the reverse-recovery loss can be significantly reduced. The operating principle of the proposed paralleling scheme is characterized by two complementary operation modes: desynchronized mode with soft-switching (lower switching loss) and synchronized mode with lower conduction loss. Compared with conventional soft-switching schemes, this solution features zero auxiliary switches, constant switching frequency, and improved full-power-range efficiency enabled by the dual operation modes. Furthermore, design guidelines of the PCI are presented where a novel winding arrangement is proposed and verified to obtain a controllable differential mode (DM) inductance. The operation principles and advantages of the proposed paralleling structure are comprehensively validated on both Buck and Boost dc-dc converters with Si/SiC power MOSFETs and diodes. Index Terms-Parallel MOSFETs, zero-voltage switching (ZVS), zero-current switching (ZCS), dual operation modes.

Design of an adaptive power controller for improving THD performance of integrated-parallel buck-boost converter via efficient reverse power routing

“…It is observed that Marx Generator has lower delay, but reduces power efficiency due to use of polarity-based output levels. Applications of these models are discussed in [11][12][13][14], wherein Current-Fed Switched Capacitors, parallel topology with energy management, Parallel coordination control of multi-port DC-DC converters, and split parallel semi bridge switching cells are developed using buck-boost converters. These models showcase lower delay with higher conversion efficiency, but have higher THD levels due to improper load and source feeding levels.…”

Hybrid-Mode Adaptive Zero-Voltage Switching for Single-Phase DC–AC Conversion With Paralleled SiC MOSFETs

“…In the practical control implementation, undesired oscillations between two operation modes may happen due to the presence of sampling noise or overshoot during the dynamic process. Therefore, the instantaneous load current i Lo at the line frequency is fed to a hysteresis block to increase the immunity to such disturbance [16]. Then, the sensed current value is feedback to the current regulator used to determine whether the CCM or QCM needs to be adapted for the minimum combined switching and conduction losses at this load current.…”

“…To address these issues of varying switching frequency while effectively suppress-ing the associated conduction loss, alternative soft-switching techniques have been proposed. In [16] and [17], a family of partial soft-switching solutions featured by quadrilateral current mode (QCM) have been proposed. These solutions are developed based on parallel-connected power transistors and manage to achieve constant switching frequency, ZCDcircuit free, and high full-load-range efficiency.…”

“…6. Comparison of loss distribution of instantaneous power loss in half line cycle between QCM and CCM at two load conditions: (a, b) half load (2.2 kW), and (c, d) full load (4.4 kW).The core and conduction loss of the inductors are calculated using iGSE and Dowell Model[16]. The switching frequency is 150 kHz and each switch is a Cree C3M00600650K SiC MOSFET (R ds,ON = 60mΩ).…”

Enabling Resonant Commutated Pole in Parallel Power FET Bridge Legs

“…To achieve better current sharing among parallel transistors, many approaches have been proposed, including active [11], [15], [16], passive [4], [12]- [14], [17]- [20] and layoutsymmetrization methods [8], [21], [22]. However, under the premise of absolute layout symmetry guaranteed, and current misharing may still occur due to the parameter mismatches of the paralleled transistors.…”