SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures

Abstract

Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their efficiency and flexibility. While many CGRAs have demonstrated impressive performance improvements, the effectiveness of CGRA platforms ultimately hinges on the compiler. Existing CGRA compilers do not model the details of the CGRA architecture, due to which they are, i) unable to map applications, even though a mapping exists, and ii) use too many PEs to map an application. In this paper, we model several CGRA details in our compiler and develop a graph mapping based approach (SPKM) for mapping applications onto CGRAs. On randomly generated graphs our technique can map on average 4.5X more applications than the previous approaches, while using fewer CGRA rows 62% times, without any penalty in mapping time. We observe similar results on a suite of benchmarks collected from Livermore Loops, Multimedia and DSPStone benchmarks.

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

“…Schedulability, in fact, sharply decreases as the size of the cut to be mapped increases, as can be seen in Fig. 14, in accordance with results shown in [20] and [36].…”

“…On each edge, the number of routing nodes must be sufficient to completely traverse the scheduling space, whose time dimension is bounded by the maximum as-late-aspossible (ALAP) among operations to be mapped [24], while its space dimension corresponds to the physical size of the reconfigurable mesh. This approach is an extension of Yoon's work [20] from a spatial to a modulo-constrained environment.…”

“…Examples of this strategy are SPKM [20] and SMP [22]. These works acknowledge the dual function (computation and data routing) of CGRA cells but, as opposed to our method, neglect the opportunity to chain routing through cells to speed up execution.…”

“…This mechanism is a feature of the EGRA [19] SPKM [20] Hatanaka [21] SMP [22] Graph embedding [23] Res. pipeline [17] Fig architectural template [12], [13], described in Section III, and used as a target of the scheduling methodology detailed in Section IV.…”

Compiling custom instructions onto expression-grained reconfigurable architectures

“…Yoon and Ahn [12,13] studied different approaches for mapping applications onto possibly heterogeneous CGRAs. Besides providing an ILP formulation of CGRA place-androute, they propose two efficient algorithms for the same problem: one first groups elements into columns, and then lays out the nodes on the grid; the other uses techniques from planar graph drawing.…”