Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Abstract

Abstract-Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than stateof-the-art approaches (as much as 38% for the benchmark applications considered).

Dataflow Modeling for Reconfigurable Signal Processing Systems

“…On the other hand, besides design and debug issues 2 , the adoption of CG reconfigurable heterogeneous and irregular platforms is limited by the fact that mapping is not so straightforward. Research efforts have been undertaken to automate the application mapping process [3]. Dimensioning the underlying hardware substrate and efficiently mapping several applications over it are key challenges that can be addressed by combining the dataflow models to the CG reconfigurable approach.…”

Power and clock gating modelling in coarse grained reconfigurable systems

“…A lot of research effort has been undertaken to automate applications and kernels mapping over CGR systems [18,2]. This problem requires a detailed knowledge of the input kernels, which normally have to be identified and then described using a hardware description language.…”

Battery-Aware Loop Nests Mapping for CGRAs

“…We use the Integrated Kernel Partitioning (IKP) in [13] and modify it for our cases. IKP can seperate the loop into several cuts, and we use S i denotes the i th cut.…”