Spin-coated $$\hbox {Cu}_2\hbox {ZnSnS}_{4}$$ solar cells: A study on the transformation from ink to film

Abstract

In this paper, we study the DMSO/thiourea/chloride salt system for synthesis of pure-sulfide $$\hbox {Cu}_2\hbox {ZnSnS}_{4}$$ Cu 2 ZnSnS 4 (CZTS) thin-film solar cells under ambient conditions. We map out the ink constituents and determine the effect of mixing time and filtering. The thermal behavior of the ink is analyzed, and we find that more than 90% of the solvent has evaporated at $$250\,^{\circ }\hbox {C}$$ 250 ∘ C . However, chloride and sulfoxide species are released continually until $$500\,^{\circ }\hbox {C}$$ 500 ∘ C , suggesting the advantage of a higher pre-annealing temperature, which is also commonly observed in the spin-coating routines in literature. Another advantage of a higher pre-annealing temperature is that the worm-like pattern in the spin-coated film can be avoided. We hypothesize that this pattern forms as a result of hydrodynamics within the film as it dries, and it causes micro-inhomogeneities in film morphology. Devices were completed in order to finally evaluate the effect of varying thermal exposure during pre-annealing. Contrary to the previous observations, a lower pre-annealing temperature of $$250\,^{\circ }\hbox {C}$$ 250 ∘ C results in the best device efficiency of 4.65%, which to the best of our knowledge is the highest efficiency obtained for a pure-sulfide kesterite made with DMSO. Lower thermal exposure during pre-annealing results in larger grains and a thicker $$\hbox {MoS}_2$$ MoS 2 layer at the CZTS/Mo interface. Devices completed at higher pre-annealing temperatures display the existence of either a Cu-S secondary phase or an incomplete sulfurization with smaller grains and a fine-grain layer at the back interface.

DMF‐Based Large‐Grain Spanning Cu2ZnSn(Sx,Se1‐x)4 Device with a PCE of 11.76%

“…To evaluate the influence of pre‐annealing temperatures on the crystallinity of the CZTS precursor films, Raman measurements were performed (Figure 1b). It is observed that the intensity of the peak at 326 cm –1 , which is the characterization peak of CZTS, [ 29 ] gradually increases and becomes sharp as the pre‐annealing temperature increases from 350 to 450 ℃, indicating the increased crystallinity. This result is also confirmed by the XRD patterns shown in Figure S2 (Supporting Information).…”

“…[12,27,31] As the pre-annealing temperature increases, the residual complex polymers in the precursor film decrease. [29,32] Complex polymers tend to hinder the diffusion of selenium vapor, so reducing the complex polymers residue will promote crystal growth during selenization. The higher the temperature, the better crystallinity of the precursor, and the larger grain size at the upper contact interface during selenization.…”

A Two-Step Magnetron Sputtering Approach for the Synthesis of Cu2ZnSnS4 Films from Cu2SnS3\ZnS Stacks

“…The reason behind the large particles obtained is the two annealing processes, because the first heat treatment was performed to obtain the CTS layer, and then a second annealing was performed after the ZnS was deposited on top of CTS. Several studies suggest the need for a preannealing followed by a sulfurization to obtain large CZTS grains . Additionally, the CTS films prepared with SnS 2 on top were characterized by voids which were totally covered by the ZnS top layer.…”

“…Several studies suggest the need for a preannealing followed by a sulfurization to obtain large CZTS grains. 75 Additionally, the CTS films prepared with SnS 2 on top were characterized by voids which were totally covered by the ZnS top layer. The elemental compositions in all the 12 films were close to the ideal stoichiometry regardless of the annealing time or atmosphere.…”

Hysteresis‐Free Planar Perovskite Solar Module with 19.1% Efficiency by Interfacial Defects Passivation

“…[33][34][35][36][37][38] In particular, spin-coating is still a favorable technique not only for conventional silicon PVs but also for emerging ones such as copper zinc tin sulfide (CZTS). [39,40] Moreover, since the dimensions of the silicon wafers, c-Si/PSC tandem technology can adopt the spin-coating technique. [41] To scale up to module size, we have optimized the PVSK composition, and the spin-coating ramping, speed, and timing (see Experimental Section) for both PVSK solution and antisolvent, since the material composition and deposition parameters optimized for small-area cells induced cracks, inhomogeneous layer, pinholes, agglomeration sites, and amorphous PVSK phase when scaled to module size (Figure S1, S2, Supporting Information).…”