Speedpath prediction based on learning from a small set of examples

Bastani, Pouria; Killpack, Kip; Wang, Li-C.; Chiprout, Eli

doi:10.1145/1391469.1391524

Cited by 45 publications

(25 citation statements)

References 6 publications

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“…For a fabricated chip, the degree of variation might be such that the delays of some of the paths exceed their timing requirements. We assume such paths are isolated and their delays are measured as discussed in [1], [3], [5], [7], [9]. Moreover, we assume the delays of additional speedpaths are also measured.…”

Section: Preliminariesmentioning

confidence: 99%

“…Note that our focus is on the segment identification problem, assuming the failing speedpaths are provided. We assume isolation of failing speedpaths is done using existing works such as [1], [3], [5], [7], while post-silicon path delay measurement is done using existing techniques such as [9].…”

Section: Problem Definitionmentioning

confidence: 99%

“…In [8], a technique is proposed to dynamically isolate failures (including timing failures) at the micro-architecture level in which the isolation is at the block-level. In [1], a statistical learning approach is proposed to predict the failing speedpaths by measuring the delays of a small set of representative paths at the post-silicon stage. To help identify such representative paths, in [3], a technique is proposed which relies on defining a set of basic features (e.g., the number or types of logic gates) to rank the target speedpaths.…”

Section: Introductionmentioning

confidence: 99%

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Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Xie

Davoodi

Saluja

2010

Proceedings of the 47th Design Automation Conference

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We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as "failing segments" and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of nonfailing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high "diagnosis resolution" in identifying failing segments, and in ranking them.

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Section: Preliminariesmentioning

confidence: 99%

Section: Problem Definitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Xie

Davoodi

Saluja

2010

Proceedings of the 47th Design Automation Conference

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“…is a key question that was raised by the authors of [1], hoping to spur more research on learning from silicon data in order to achieve better silicon-to-model correlation. Indeed, this question touches on the widely accepted reality, that silicon speed-limiting paths, or simply silicon speedpaths, are not always accurately predicted by existing timing flows [2]. This can be attributed to a number of effects, including process, design, or environmental effects, that are either not fully understood or too difficult to model in modern designs.…”

Section: Introductionmentioning

confidence: 99%

“…The delays of the paths from silicon are not used in the analysis, and the authors do not try to reconcile actual measurements with the models. On the other hand, the authors of [2] employ a machine-learning approach that uses a small number of identified speedpaths to predict a larger set of paths that are potentially speed-limiting. They do this without identifying the root causes, which they say saves time and reduces the time to market.…”

Section: Introductionmentioning

confidence: 99%

PSTA-based branch and bound approach to the silicon speedpath isolation problem

Onaissi

Heloue

Najm

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The identification of speedlimiting paths, or simply speedpaths, in silicon debug is a crucial step, required for both "fixing" failing paths and for accurate learning from silicon data. We propose using characterized, presilicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements. Delays of all logic paths are written as affine functions of process parameters, called hyperplanes, and a branch and bound approach is then applied to find the "best" path combinations. Our method has been tested on a set of ISCAS-89 circuits and the results show that it accurately identifies the speedpaths in most cases, and that this is achieved in a very efficient manner.

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Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells

Melikyan

2023

Machine Learning-Based Design and Optimization of High-Speed Circuits

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Speedpath prediction based on learning from a small set of examples

Cited by 45 publications

References 6 publications

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

PSTA-based branch and bound approach to the silicon speedpath isolation problem

Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells

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