Spectroscopic and electrical properties of ultrathin SiO2 layers formed with nitric acid

Asuha,; Kobayashi, Takuya; Takahashi, Masatoshi; Iwasa, Hitoo; Kobayashi, Hikaru

doi:10.1016/j.susc.2003.09.016

Cited by 46 publications

(27 citation statements)

References 30 publications

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“…While the POA treatment eliminates some suboxide species, which is the reason for the decrease of the leakage current density [3], the PMA treatment should form the Si-H bonds from Si dangling bonds by the reaction with atomic hydrogen. This is produced by the catalytic activity of the Al electrode, but also can likely react with other defects [2].…”

Section: Discussionmentioning

confidence: 99%

“…Recently, the nitric acid (HNO 3 ) oxidation method of Si (NAOS), which can be performed at relatively low temperatures (∼120°C), was developed [1][2][3]. Using the chemical SiO 2 layers formed in HNO 3 , the formation of ultrathin * E-mail: bury@fel.uniza.sk SiO 2 layers with a leakage current density much lower than those of thermally grown SiO 2 layers, or layers prepared by a different chemical oxidation procedure with the same thickness [2], can be performed.…”

Section: Introductionmentioning

confidence: 99%

“…Using the chemical SiO 2 layers formed in HNO 3 , the formation of ultrathin * E-mail: bury@fel.uniza.sk SiO 2 layers with a leakage current density much lower than those of thermally grown SiO 2 layers, or layers prepared by a different chemical oxidation procedure with the same thickness [2], can be performed. Although the density of interface states present at SiO 2 /Si interfaces is usually low, it can seriously affect the electrical characteristics of metal-oxide-semiconductor (MOS) devices.…”

Section: Introductionmentioning

confidence: 99%

“…The leakage current density and consequently the interface state density can be decreased by a post oxidation annealing (POA) treatment in a nitrogen atmosphere [3] and/or a post-metallization annealing (PMA) treatment in a hydrogen atmosphere [2,5].…”

Section: Introductionmentioning

confidence: 99%

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Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Bury¹,

Kobayashi²,

Takahashi³

et al. 2009

Open Physics

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Abstract:Ultrathin silicon dioxide (SiO 2 ) layers formed on Si substrate with nitric acid have been investigated using both acoustic deep-level transient spectroscopy (A-DLTS) and electrical methods to characterize the interface states. The set of SiO 2 /Si structures formed in different conditions (reaction time, concentrations of nitric acid (HNO 3 ), and SiO 2 thickness [3-9 nm]) was prepared. The leakage current density was decreased by post-oxidation annealing (POA) treatment at 250°C in pure nitrogen for 1 h and/or post-metallization annealing (PMA) treatment at 250°C in a hydrogen atmosphere for 1 h. All structures of the set, except electrical investigation, current-voltage (I − V ), and capacitance -voltage (C − V ) measurements, were investigated using A-DLTS to find both the interface states distribution and the role of POA and/or PMA treatment on the interface-state occurrence and distribution. The evident decreases of interface states and shift of their activation energies in the structures with PMA treatment in comparison with POA treatment were observed in most of the investigated structures. The results are analyzed and discussed. PACS (2008):73.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Bury¹,

Kobayashi²,

Takahashi³

et al. 2009

Open Physics

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“…[20][21][22][23][24][25][26][27][28] TFTs with a gate oxide of 20 and 40 nm thickness with a NAOS SiO 2 layer have decreased the z E-mail: h.kobayashi@sanken.osaka-u.ac.jp dynamic consumption to 1/16 and 1/64 (1/V 2 reduction) of that for the current commercial TFTs with 12 V driving voltage, respectively. 26,27 In the present study, we have demonstrated that the driving voltage of 1 V is realized by a decrease in the gate oxide thickness to 10 nm (cf.…”

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confidence: 99%

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

Matsumoto

Tsuji

Terakawa

et al. 2015

ECS J. Solid State Sci. Technol.

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We have fabricated poly-silicon-based thin film transistors (TFTs) on glass substrates, and achieved ultra-low power consumption by driving at 1 V. The gate oxide layer has a 10 nm thick stacked structure with a 1.4 nm interfacial SiO 2 layer formed by the nitric acid oxidation of silicon (NAOS) method and a 8.6 nm SiO 2 layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. The dynamic power consumption ratio of the NAOS-TFTs is 1/144 of that for the currently commercial TFTs with the driving voltage of 12 V and 80 nm gate oxide. The off-current decreases by ∼2 orders of magnitude by insertion of the ultra-thin NAOS SiO 2 layer. The off-current decrease is attributed to i) blocking of the gate leakage current by the NAOS SiO 2 layer, and ii) improvement of the quality of the deposited oxide on the NAOS SiO 2 layer because of better nucleation, and consequently, the high on/off ration exceeding 10 9 is achieved. Low power consumption is one of the most important issues for mobile products with batteries. System liquid crystal displays (LCDs) are widely used for popular mobile electronic products such as smart phones, e-books, and personal digital assistance (PDAs) because of their low power consumption.The dynamic consumed power of a TFT, P, is expressed aswhere f is a signal frequency, C is a charging and discharging capacitance, and V is a driving voltage. Therefore, the consumed power can be decreased most effectively by reducing the driving voltage, which is approximately proportional to a gate oxide thickness. The decrease in the gate insulator thickness makes it possible not only to decrease the consumed power but also to miniaturize TFTs, which greatly improves electrical characteristics of TFTs. 2Thermal oxidation is unavailable for TFT production because of the use of glass substrates with low softening temperature of ∼500• C. Consequently, a gate oxide layer in poly-crystalline Si (poly-Si)-based TFTs is usually formed by the plasma-enhanced chemical vapor deposition (PECVD) method using tetraethyl orthosilicate (TEOS). [3][4][5][6] However, deposition methods have following demerits: i) interface state densities are high due to incomplete interfacial chemical bonds and presence of contaminants before deposition, 7,8 ii) bulk characteristics are poor due to imperfect structure including small SiO 2 particles which were originally formed in the gas phase and C and OH contaminants, 9,10 and due to poor nucleation of an SiO 2 layer on polySi surfaces compared to that on oxide surfaces, iii) the oxide layer thickness is not uniform on rough poly-Si surfaces due to formation of ridge structure arising from laser annealing of amorphous-Si (a-Si) films to crystallize. 11Extensive studies have been performed for developing direct Si oxidation methods at low temperatures including plasma oxidation, 12,13 photo-oxidation, 14,15 ozone oxidation, 16,17 metalpromoted oxidation, 18,19 etc. We have developed a low temperature direct Si oxidation method, i.e., the chemical oxidation method called ...

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Improved Interface and Electrical Properties by Inserting an Ultrathin SiO₂ Buffer Layer in the Al₂O₃/Si Heterojunction

Kim

Choi

Ryu

et al. 2019

Adv Funct Materials

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An ultrathin SiO 2 interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al 2 O 3 /Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al 2 O 3 /Si sample (8.1 × 10 −9 A cm −2 ) due to the formation of low-density SiO x layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO 2 buffer layer is inserted using the NAOS method (1.1 × 10 −11 A cm −2 ), and further decreases after post-metallization annealing (PMA) (1.4 × 10 −12 A cm −2 ). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (N d ) and fixed charge density (N f ) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (D it ) at 0.11 eV decreases about one order of magnitude from 2.5 × 10 12 to 7.3 × 10 11 atoms eV −1 cm −2 after NAOS, and to 3.0 × 10 10 atoms eV −1 cm −2 after PMA. Consequently, it is demonstrated that the high defect density of the Al 2 O 3 /Si interface is drastically reduced by fabricating ultrathin high density SiO 2 buffer layer, and the insulating properties are improved.The ORCID identification number(s) for the author(s) of this article can be found under https://doi.

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Spectroscopic and electrical properties of ultrathin SiO2 layers formed with nitric acid

Cited by 46 publications

References 30 publications

Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO₂ Buffer Layer in the Al₂O₃/Si Heterojunction

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Spectroscopic and electrical properties of ultrathin SiO2 layers formed with nitric acid

Cited by 46 publications

References 30 publications

Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Acoustic spectroscopy and electrical characterization of SiO2/Si structures with ultrathin SiO2 layers formed by nitric acid oxidation

Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

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Product

Resources

About

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO₂ Buffer Layer in the Al₂O₃/Si Heterojunction