Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

Kim, Doyeon; Choi, Jae-Ho; Ryu, Sang-Ouk; Kim, Woo‐Byoung

doi:10.1002/adfm.201807271

Cited by 9 publications

(1 citation statement)

References 40 publications

(49 reference statements)

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“…Previously, researchers decreased dielectric leakage by enhancing high-κ material interface contact with semiconductors by adding additional metal interlayers or building a gate-stack structure [18][19][20]. For example, Kim et al enhanced the dielectric/semiconductor interface by introducing an ultrathin SiO 2 buffer layer in the Al 2 O 3 /Si heterojunction and achieved a low EOT of 2.5 nm [21]. Kambayashi et al also fabricated high quality SiO 2 /Al 2 O 3 gate stack for the GaN MOSFET [22].…”

Section: Introductionmentioning

confidence: 99%

Ultimate low leakage and EOT of high-κ dielectric using transferred metal electrode

Dang¹,

Lu²,

Zhao³

et al. 2022

Nanotechnology

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The increase of gate leakage current when the gate dielectric layer is thinned is a key issue for device scalability. For scaling down the integrated circuits, a thin gate dielectric layer with a low leakage current is essential. Currently, changing the dielectric layer material or enhancing the surface contact between the gate dielectric and the channel material is the most common way to reduce gate leakage current in devices. Herein, we report a technique of enhancing the surface contact between the gate dielectric and the metal electrode, that is constructing an Au/Al2O3/Si metal–oxide–semiconductor device by replacing the typical evaporated electrode/dielectric layer contact with a transferred electrode/high-κ dielectric layer contact. The contact with a mild, non-invasive interface can ensure the intrinsic insulation of the dielectric layer. By applying 2–40 nm Al2O3 as the dielectric layer, the current density–electrical field (J–E) measurement reveals that the dielectric leakage generated by the transferred electrode is less than that obtained by the typical evaporated electrode with a ratio of 0.3 × 101 ∼ 5 × 106 at V bias = 1 V. Furthermore, at J = 1 mA cm−2, the withstand voltage can be raised by 100–102 times over that of an evaporated electrode. The capacitance–voltage (C–V) test shows that the transferred metal electrode can efficiently scale the equivalent oxide layer thickness (EOT) to 1.58 nm, which is a relatively smaller value than the overall reported Si-based device’s EOT. This finding successfully illustrates that the transferred electrode/dielectric layer’s mild contact can balance the scaling of the gate dielectric layer with a minimal leakage current and constantly reduce the EOT. Our enhanced electrode/dielectric contact approach provides a straightforward and effective pathway for further scaling of devices in integrated circuits and significantly decreases the overall integrated circuit’s static power consumption (ICs).

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