SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance

Aslot, Vishal; Domeika, Max; Eigenmann, Rudolf; Gaertner, Greg; Jones, Wesley B.; Parady, Bodo

doi:10.1007/3-540-44587-0_1

Cited by 145 publications

(118 citation statements)

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“…Apart from our synthetic benchmark, we have run a number of SPEC OMP [3] benchmarks on our emulator. Unless specified otherwise, OpenMP compilers divide parallel work evenly among available processors.…”

Section: B Spec Omp Benchmarksmentioning

confidence: 99%

Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

Morad

Weiser

Kolodnyt³

et al. 2006

IEEE Comput. Arch. Lett.

123

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Abstract-This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large high-performance cores whereas parallel phases are executed on a mix of large and many small simple cores. Theoretical analysis reveals a performance upper bound for symmetric multiprocessors, which is surpassed by asymmetric configurations at certain power ranges. Our emulations show that asymmetric multiprocessors can reduce power consumption by more than two thirds with similar performance compared to symmetric multiprocessors.

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Section: B Spec Omp Benchmarksmentioning

confidence: 99%

Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

Morad

Weiser

Kolodnyt³

et al. 2006

IEEE Comput. Arch. Lett.

123

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“…We configured it to model a multi-core out-of-order processor resembling the Intel Nehalem processor, see Table I for its main characteristics. The benchmark suites used in this paper are the SPEC OpenMP (medium) suite (train inputs) [3], the NAS Parallel Benchmarks version 3 with OpenMP parallelization (class A inputs) [13], and the PARSEC 2.1 benchmark suite (simlarge inputs) [5]. We refer to the benchmarks from these suites using the O-* , N-* and P-* notations, respectively.…”

Section: Experimental Setup a Simulation Configurationmentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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“…•ART the Open MP version of the SPEC 2000 ART benchmark which forms part of the SPEC OMP 2001 suite [21]. This has a read to write ratio of around 2:1.…”

Section: •Svm-rfe (Support Vector Machines Recursivementioning

confidence: 99%