Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

Abstract

Abstract-This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large high-performance cores whereas parallel phases are executed on a mix of large and many small simple cores. Theoretical analysis reveals a performance upper bound for symmetric multiprocessors, which is surpassed by asymmetric configurations at certain power ranges. Our emulations show that asymmetric multiprocessors can reduce power consumption by more than two thirds with similar performance compared to symmetric multiprocessors.

Amdahl's Law in the Multicore Era

“…Furthermore, scheduling software tasks on asymmetric and dynamic multicore chips could be difficult and add overhead. To this end, Tomer Morad and his colleagues 13 and JoAnn Paul and Brett Meyer 14 developed sophisticated models that question the validity of Amdhal's law to future systems, especially embedded ones. On the other hand, more cores might advantageously allow greater parallelism from larger problem sizes, as John Gustafson envisioned.…”

A cost conscious performance model for media processors

“…The power can be various by employing different VLSI technology, optimization techniques and design methodology. We simplify this problem by assuming that total architecture power is proportional to the overall area (shown in equation (7)), as proposed in [4].…”

Understanding performance, power and energy behavior in asymmetric multiprocessors

“…Many researchers have shown that asymmetric/heterogeneous multi-core/multiprocessor architectures can save power and energy [3], [13], [1], [15]. Since the focus of our work is evaluation of the behavior of multithreaded applications in a real system, we only discuss previous work that also use real heterogeneous/asymmetric systems.…”

“…Asymmetric multiprocessor architectures have been proposed to be power efficient multiprocessor architectures [3], [13], [1], [15]. Research has shown that these architectures provide power-performance effective platforms for both throughput-oriented applications and applications that would benefit from having high performance processors.…”