Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling

Ganesh, Brinda; Jaleel, Aamer; Wang, D.; Jacob, Bruce

doi:10.1109/hpca.2007.346190

Cited by 67 publications

(34 citation statements)

References 14 publications

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“…A bank lowers all wordlines by broadcasting an IN V (invalid) value on the global row-address bus. 9 However, when there are two activated subarrays (each with a raised wordline) SALP-2 needs to be able to selectively precharge only one of the subarrays. To achieve this, we require that PRECHARGEs be issued with the corresponding subarray ID.…”

Section: Salp-2: Per-subarray Row-address Latchesmentioning

confidence: 99%

“…Second, one can increase the number of banks in a channel by multiplexing the channel with many memory modules, each of which is a collection of banks. Unfortunately, this increases the electrical load on the channel, causing it to run at a significantly reduced frequency [8,9]. Third, one can add more memory channels to increase the overall bank count.…”

Section: Introductionmentioning

confidence: 99%

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A case for exploiting subarray-level parallelism (SALP) in DRAM

Kim

Seshadri

Lee

et al. 2012

SIGARCH Comput. Archit. News

148

223

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Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the high latency of off-chip memory. Adding more banks to the system to mitigate this problem incurs high system cost. Our goal in this work is to achieve the benefits of increasing the number of banks with a low cost approach. To this end, we propose three new mechanisms that overlap the latencies of different requests that go to the same bank. The key observation exploited by our mechanisms is that a modern DRAM bank is implemented as a collection of subarrays that operate largely independently while sharing few global peripheral structures.Our proposed mechanisms (SALP-1, SALP-2, and MASA) mitigate the negative impact of bank serialization by overlapping different components of the bank access latencies of multiple requests that go to different subarrays within the same bank. SALP-1 requires no changes to the existing DRAM structure and only needs reinterpretation of some DRAM timing parameters. SALP-2 and MASA require only modest changes (< 0.15% area overhead) to the DRAM peripheral structures, which are much less design constrained than the DRAM core. Evaluations show that all our schemes significantly improve performance for both single-core systems and multi-core systems. Our schemes also interact positively with applicationaware memory request scheduling in multi-core systems.

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Section: Salp-2: Per-subarray Row-address Latchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A case for exploiting subarray-level parallelism (SALP) in DRAM

Kim

Seshadri

Lee

et al. 2012

SIGARCH Comput. Archit. News

148

223

View full text Add to dashboard Cite

show abstract

“…To further increase capacity, we present a new module architecture for LPDDR2, which draws lessons from registered/buffered DDR3. We can also scale channel and socket counts [2,11]. Finally, we describe error correction for this system.…”

Section: Architecting Mobile Dramsmentioning

confidence: 99%

Towards energy-proportional datacenter memory with mobile DRAM

Malladi

Lee

Nothaft

et al. 2012

SIGARCH Comput. Archit. News

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To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3× the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5× lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

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“…We propose two new schemes and evaluate their effectiveness on systems with multicore processors and Fully Buffered DIMM (FBDIMM) memories [11]. The first scheme, Adaptive Core Gating, applies clock gating on selected processor cores according to the DRAM thermal state.…”

Section: Integrated Thermal Model Of Fbdimmmentioning

confidence: 99%