Specifying Hardware Systems in Lotos

Faci, Mohammed; Logrippo, Luigi

doi:10.1016/b978-0-444-81641-2.50028-9

Cited by 10 publications

(9 citation statements)

References 13 publications

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“…To specify hardware circuits formally, the description techniques LOTOS [1,12], Estelle [15] and SDL [13] have been proposed. With these techniques, we can easily describe schemes for hardware circuits using predefined component libraries, and can verify/validate them.…”

Section: Introductionmentioning

confidence: 99%

Hardware Synthesis from Protocol Specifications in LOTOS

Yasumoto

Kitajima

Higashino

et al. 1998

IFIP Advances in Information and Communication Technology

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In this paper, we propose a technique for hardware implementation of protocol specifications in LarOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LaroS. The derived synchronous EFSMs can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock. By applying our technique to the Abracadabra protocol, it is confirmed that the derived circuit handles multi-rendezvous efficiently.

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Section: Introductionmentioning

confidence: 99%

Hardware Synthesis from Protocol Specifications in LOTOS

Yasumoto

Kitajima

Higashino

et al. 1998

IFIP Advances in Information and Communication Technology

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“…The initial work at Stirling [25] overlapped independent work in Ottawa [6]. The European project FORMAT [5] studied the translation of LOTOS to VHDL.…”

Section: Hardware Description and Verificationmentioning

confidence: 99%

Specification and Verification of Synchronous Hardware using LOTOS

Turner

1999

IFIP Advances in Information and Communication Technology

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Abstract:This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Ca:sar/Aldebaran Development Package).

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“…The LOTOS language has been selected for the formal specification of the BULL'S CC_NUMA architecture because its underlying semantics model is based on the rendez-vous synchronization mechanism which is well suited for the specification of hardware entities [4,5] such as processors, memory controllers, bus arbiter, etc. The communications between these components by sending electrical signals on conductors are better described by interactions between LOTOS processes, rather than infinite FIFO queues as in SDL.…”

Section: Formal Specification Of the Cache Coherency Protocolmentioning

confidence: 99%

An industrial experiment in automatic generation of executable test suites for a cache coherency protocol

Kahlouche

Viho

Zendri³

1998

Testing of Communicating Systems

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In this paper, we present an end-to-end industrial case-study concerning the automatic generation of tests suites for the Cache Coherency Protocol of a Multiprocessor Architecture. It consists of the following stages: (1) formal specification of the architecture using Lotos language, (2) formal description of the test purposes, (3) automatic generation of abstract test suites using the prototype TGV, and (4) automatic generation and analysis of executable test suites. Through the description of each of the previous stages, this paper demonstrates that tools designed for protocol conformance testing can be efficiently used to generate executable tests for hardware concurrent systems.

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Specifying Hardware Systems in Lotos

Cited by 10 publications

References 13 publications

Hardware Synthesis from Protocol Specifications in LOTOS

Hardware Synthesis from Protocol Specifications in LOTOS

Specification and Verification of Synchronous Hardware using LOTOS

An industrial experiment in automatic generation of executable test suites for a cache coherency protocol

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