Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Du, Yuelin; Ma, Qiang; Song, Hua; Shiely, James P.; Luk-Pat, Gerard; Miloslavsky, Alexander; Wong, D.F.

doi:10.1145/2463209.2488848

Cited by 31 publications

(31 citation statements)

References 13 publications

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“…To date, manufacturing-friendly detailed routing studies follow the paradigms of sequential routing [11], [13], [28], [37], [45], [46] and negotiation-congestion-based routing technique [8], [9]. When a router accesses an I/O pin locally, it creates a routing interval pattern on M2 for the net connection as shown in Fig.…”

Section: Pin Access Planningmentioning

confidence: 99%

“…Most existing manufacturing-friendly studies focus on the coloring scheme of routing patterns while leveraging SAMP-specific manufacturing constraints [8], [9], [11], [13], [28], [37], [45], c 2017 Information Processing Society of Japan [46], [57], [68]. Reference [45] presents the first SADP-aware detailed routing study by considering SADP-specific constraints during sequential routing procedure.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

“…Refereces [28], [29] focus on novel grid coloring techniques to guarantee SADP and SAQP friendliness during routing. Reference [9] proposes a novel graph model to capture the SADP-specific manufacturing constraints and delivers SADP-friendly routing results with negotiation-congestion-based routing scheme. References [37] and [8] further enhance the graph model for better results by considering overlay constraints and via model, respectively.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Section: Pin Access Planningmentioning

confidence: 99%

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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“…Double patterning technology (DPL) [5], [12], [20], [21], [23], [24], [28] is already reaching its limit at 20nm technology node [2]. Beyond 20nm technology node, next generation lithography such as Extreme Ultraviolet Lithography (EUVL) and E-beam, or multiple patterning techniques have to be utilized to conquer these manufacturing difficulties.…”

Section: Introductionmentioning

confidence: 99%

Constrained pattern assignment for standard cell based triple patterning lithography

Tian

Xiao

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Triple patterning lithography (TPL) has been recognized as one of the most promising candidates for 14/10nm technology node. Apart from obtaining legal TPL decompositions, various concerns have been raised by the designers, among them consistently assigning the same pattern for the same type of standard cells and balancing the usage of the three masks are two most critical ones. In this paper, a hybrid approach (SAT followed by a sliding-window approach) is proposed targeting at these two problems. To assign the same pattern for the same type of standard cell, we pre-color the boundary polygons of each type of cell by solving a small SAT problem. Following that we propose a sliding-window based approach to compute a locally balanced decomposition. Our algorithm guarantees to find a feasible solution if one exists. Experimental results verify that the problem can be solved very efficiently with the proposed algorithm. Superior locally balanced decompositions are achieved compared with the previous approach in [19].

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“…To incorporate SADP constraints into early design stages, there are several studies [11]- [14] dealing with the SADPaware routing problem. However, to date, works studying how multiple patterning and decomposition impact SC I/O pin design are lacking, especially as pin congestion and routability become increasingly critical to the overall physical design results.…”

mentioning

confidence: 99%

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

Cline

Yeric

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to ∼50 nm because it has better line edge roughness and overlay control compared to other multiple patterning candidates. To date, most of the SADPrelated literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. At the same time, via layers are used to connect the local SADP routing layers to the I/O pins on lower metal layers. Due to the high via density on the Via-1 layer, the litho-etch-litho-etch (LELE)-aware Via-1 design becomes a necessity to achieve legal pin access at the SC level. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific and Via-1 design rules, we propose a coherent framework that uses depth first search, mixed integer linear programming, and backtracking method to enable LELE friendly Via-1 design and simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the SCs and maximizes the pin access flexibility for routing.Index Terms-Double patterning, pin access, self-aligned double patterning (SADP), standard cell (SC) layout, Via-1 assignment.

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Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Cited by 31 publications

References 13 publications

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Constrained pattern assignment for standard cell based triple patterning lithography

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

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