Source level debugger for the Sea Cucumber synthesizing compiler

Hemmert, Karl Scott; Tripp, Justin L.; Hutchings, Brad; Jackson, Preston A.

doi:10.1109/fpga.2003.1227258

Cited by 36 publications

(27 citation statements)

References 6 publications

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“…Furthermore, since the design is implemented on an FPGA, it is possible to run the testbed on-chip to verify the behaviour of CEs with a large number of data packets to obtain quick and accurate results. Previous work demonstrated that debugging [11,12] and profiling [10] designs using on-chip resources results in a significant reduction of the time required to obtain information for the designer. Since design verification commonly requires greater than 50% of the overall design time, sometimes as much as 70% [13], it may be possible to reduce the percentage of time spent verifying the design, and thus reduce the overall design time.…”

Section: On-chip Testbedmentioning

confidence: 99%

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

Shannon

Fort

Parikh

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols between processing elements (PEs) using PE-specific SIMPPL controllers. The implementation of a real-time MPEG-1 video decoder using SIMPPL provides a practical demonstration of how the complexity of system-level design issues are reduced by enabling rapid system-level integration and on-chip verification. The adaptation of the MPEG-1 PEs into the SIMPPL framework combined with the systemlevel integration was accomplished in 72.5 hours, which is only 4.5% of the overall system design time, instead of the more typical system integration times that can be as much as 30% of the design time.

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Section: On-chip Testbedmentioning

confidence: 99%

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

Shannon

Fort

Parikh

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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show abstract

“…However, the results presented by these tools are not at the source level of HLS tools. A source-level debugger has been built for the Sea Cucumber synthesizing compiler [16] that enables breakpoints and monitoring of variables in FPGAs. Our work is complementary by enabling HLL assertions and can be potentially be used with any HLS tool.…”

Section: Related Researchmentioning

confidence: 99%

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Curreri

Stitt

George

2011

International Journal of Reconfigurable Computing

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Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy registertransfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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“…However, current commercial application mappers provide few (if any) runtime tools to debug or analyze application performance at the HLL source-code level while executing on one or more FPGAs. While methods and tools for debugging FPGAs have been well researched and even developed, such as for the Sea Cucumber HLL which has tool support for runtime debugging [3], research is currently lacking in runtime performance analysis tools for FPGAs, especially when HLLs are featured.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing

Curreri

Koehler

Holland

et al. 2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

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Source level debugger for the Sea Cucumber synthesizing compiler

Cited by 36 publications

References 6 publications

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing

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