Source/drain engineering for MOSFETs with embedded-Si:C technology

Itokawa, Hiroshi; Yasutake, N.; Kusunoki, N.; Okamoto, Shintaro; Aoki, Naofumi; Mizushima, Ichiro

doi:10.1016/j.apsusc.2008.02.176

Cited by 14 publications

(7 citation statements)

References 8 publications

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“…In approach A, both etchant gas (HCl) and dopant [P] gas are simultaneously flown to the chamber along with Silicon precursor. The HCl competes in reaction and therefore reduces the [P] incorporation -consistent with previous studies 7 . It is noted that with approach A -it is possible to reduce the nitride residual effect, however the lower dopant incorporation to substitution sites is observed.…”

Section: Resultssupporting

confidence: 84%

“…Figure 7a shows the process results using approach A; defects are observed as the thickness is increased (shaped as a triangle). Additionally selectivity is achieved by adding HCl (etchant gas) which reduces dopant incorporation 7 . In approach A, both etchant gas (HCl) and dopant [P] gas are simultaneously flown to the chamber along with Silicon precursor.…”

Section: Resultsmentioning

confidence: 99%

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NMOS SiP Epitaxy Process - Optimizing Facet Growth

et al. 2013

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Phosphorous doped selective epitaxial technology has gained interest recently as the source / drain for NMOS. High, >1E20 atm./cc., Phosphorous doping is required to ensure low contact resistance when metal contacts are formed. The study of contact resistance as a function of temperature and chemical composition of reactants is presented in this paper. Additionally, the phosphorous growth needs to have a facet to prevent any nitride residue during the remaining process flows. In this paper, the faceted growth of high Phosphorous doped Silicon epitaxy using various process schemes is explored.

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Section: Resultssupporting

confidence: 84%

Section: Resultsmentioning

confidence: 99%

NMOS SiP Epitaxy Process - Optimizing Facet Growth

et al. 2013

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“…17 In this paper, we report on the analysis by dark-field holography of the strain distribution in n-MOSFETs with recessed sources and drains of carbon-doped silicon. The measurement of strain in such devices 10,20,21 is more challenging than for SiGe/Si systems, as the lattice mismatches are significantly smaller. We will also demonstrate a recent improvement in the precision and field of view of the technique.…”

mentioning

confidence: 99%

Strain mapping of tensiley strained silicon transistors with embedded Si1−yCy source and drain by dark-field holography

Hüe

Hÿtch

Houdellier

et al. 2009

Applied Physics Letters

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Dark-field holography, a new transmission electron microscopy technique for mapping strain distributions at the nanoscale, is used to characterize strained-silicon n-type transistors with a channel width of 65 nm. The strain in the channel region, which enhances electron mobilities, is engineered by recessed Si0.99C0.01 source and drain stressors. The strain distribution is measured across an array of five transistors over a total area of 1.6 μm wide. The longitudinal tensile strain reaches a maximum of 0.58%±0.02% under the gate oxide. Theoretical strain maps obtained by finite element method agree well with the experimental results.

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“…18 This difficulty arises because the strain field in the channel region induced by silicide (CoSi 2 ) is relatively weak; 19,20 the strain fields in channels of silicide devices are on the order of 0.1 ∼ 0.2% 19,20 whereas strain fields channels of transistors with SiC stressors are about 0.5 ∼ 0.6%. 18,21,22 A TEM specimen was prepared for strain measurements using a focused ion beam (FEI Helios-450S) with a gallium source. In order to minimize the thin film effect, 14 the specimen was fabricated to be relatively thick; the thickness of the specimen was estimated by electron energy loss spectroscopy as proposed by Egerton, 23 and it was measured to be roughly ∼250 nm.…”

Section: Methodsmentioning

confidence: 99%

Reproducible strain measurement in electronic devices by applying integer multiple to scanning grating in scanning moiré fringe imaging

et al. 2014

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Scanning moiré fringe (SMF) imaging by high-angle annular dark field scanning transmission electron microscopy was used to measure the strain field in the channel of a transistor with a CoSi2 source and drain. Nanometer-scale SMFs were formed with a scanning grating size of ds at integer multiples of the Si crystal lattice spacing dl (ds ∼ ndl, n = 2, 3, 4, 5). The moiré fringe formula was modified to establish a method for quantifying strain measurement. We showed that strain fields in a transistor measured by SMF images were reproducible with an accuracy of 0.02%.

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Source/drain engineering for MOSFETs with embedded-Si:C technology

Cited by 14 publications

References 8 publications

NMOS SiP Epitaxy Process - Optimizing Facet Growth

NMOS SiP Epitaxy Process - Optimizing Facet Growth

Strain mapping of tensiley strained silicon transistors with embedded Si1−yCy source and drain by dark-field holography

Reproducible strain measurement in electronic devices by applying integer multiple to scanning grating in scanning moiré fringe imaging

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