SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing

Sousa, Miguel de Abreu de Angelo; Pires, Ricardo; Del-Moral-Hernandez, Emílio

doi:10.1016/j.neunet.2020.02.019

Cited by 23 publications

(15 citation statements)

References 43 publications

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“…Kechiche (Kechiche, 2018) shows a typical implementation that uses an ARM processor connected to an AXI bus, and making use of a 1-Gigabit DDR3 external RAM device. Sousa (Sousa, 2020) uses the million of connection updates per second (MCUPS) metric to characterize the throughput of their neural-network based application, which is different from the video processing throughput. Park (Park, 2020) discussed a 29×29-pixel Retinex algorithm at length and reported that the latency in a 1080p video processing environment at 60 fps is unnoticeable.…”

Section: Literature Reviewmentioning

confidence: 99%

Video Chunk Processor: Low-Latency Parallel Processing of 3 x 3-pixel Image Kernels

Kho¹,

Fauzi²,

Lim³

2022

IJTech

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Video framebuffers are usually used in video processing systems to store an entire frame of video data required for processing. These framebuffers make extensive use of random access memory (RAM) technologies and interfaces that use them. Recent trends in the high-speed video discuss the use of higher speed memory interfaces such as DDR4 (double-datarate 4) and HBM (high-bandwidth memory) interfaces. To meet the demand for higher image resolutions and frame rates, larger and faster framebuffer memories are required. While it is not feasible for software to read and process parts of an image quickly and efficiently enough due to the high speed of the incoming video, a hardware-based video processing solution poses no such limitation. Existing discussions involve the use of framebuffers even in hardware-based implementations, which greatly reduces the speed and efficiency of such implementations. This paper introduces hardware techniques to read and process kernels without the need to store the entire image frame. This reduces the memory requirements significantly without losing the quality of the processed images.

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Section: Literature Reviewmentioning

confidence: 99%

Video Chunk Processor: Low-Latency Parallel Processing of 3 x 3-pixel Image Kernels

Kho¹,

Fauzi²,

Lim³

2022

IJTech

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“…In some special cases, it may also lead to the emergence of “dead” neurons, thereby reducing the convergence speed and clustering accuracy of the network calculation. Therefore, the SOM network has a greater dependence on the setting of the initial weight, which will affect the convergence speed and learning effect of the network [ 35 , 36 ].…”

Section: Som Optimized By Improved Sparrow Search Algorithmmentioning

confidence: 99%

A Data Collection Strategy for Heterogeneous Wireless Sensor Networks Based on Energy Efficiency and Collaborative Optimization

Cao

Yue

Zhang

2021

Computational Intelligence and Neuroscience

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In the clustering routing protocol, prolonging the lifetime of the sensor network depends to a large extent on the rationality of the cluster head node selection. The selection of cluster heads for heterogeneous wireless sensor networks (HWSNs) does not consider the remaining energy of the current nodes and the distribution of nodes, which leads to an imbalance of network energy consumption. A strategy for selecting cluster heads of HWSNs based on the improved sparrow search algorithm- (ISSA-) optimized self-organizing maps (SOM) is proposed. In the stage of cluster head selection, the proposed algorithm establishes a competitive neural network model at the base station and takes the nodes of the competing cluster heads as the input vector. Each input vector includes three elements: the remaining energy of the node, the distance from the node to the base station, and the number of neighbor nodes of the node. The best cluster head is selected through the adaptive learning of the improved competitive neural network. When selecting the cluster head node, comprehensively consider the remaining energy, the distance, and the number of times the node becomes a cluster head and optimize the cluster head node selection strategy to extend the network life cycle. Simulation experiments show that the new algorithm can reduce the energy consumption of the network more effectively than the basic competitive neural network and other algorithms, balance the energy consumption of the network, and further prolong the lifetime of the sensor network.

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“…Tal comparação é importante porque, embora semelhantes, as computações utilizadas na implementação do algoritmo neural em FPGA não são idênticas às computações realizadas em software. Diferem-se os cálculos, implementados em ponto fixo ao invés de ponto flutuante, e a utilização da distância de Manhattan para definição do neurônio vencedor, ao invés da distância Euclidiana [Sousa et al 2020].…”

Section: Metodologiaunclassified

“…Implementações em hardware beneficiam-se do cálculo da distância de Manhattan por não necessitarem de divisões e de radiciações [Sousa 2018]. Entretanto, alguns trabalhos matemáticos sugerem que, em tarefas de agrupamento de dados (como as executadas pelo SOM), a distância de Manhattan realiza melhores avaliações da relevância de pequenas distâncias com o aumento do número de dimensões do vetor analisado [Sousa et al 2020].…”

Section: Quantidade De Janelas Analisadasunclassified

Previsão de surtos epiléticos usando Mapas Auto Organizáveis executados diretamente em hardware

Santos¹,

Nakamura²,

Santos³

et al. 2020

Anais Do Brazilian E-Science Workshop (BRESCI 2020)

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A epilepsia é uma condição neurológica que afeta o cérebro e torna os pacientes mais suscetíveis a convulsões recorrentes. Este trabalho tem como objetivo implementar um circuito lógico em FPGA (Field Programmable Gate Array) para execução de Self-Organizing Maps (SOM) aplicado na previsão de surtos epiléticos a partir de sinais de eletroencefalograma (EEG). Embora similares, as etapas de processamento executadas em hardware não são necessariamente idênticas às executadas em software. Os resultados obtidos foram comparados ao trabalho anterior, o qual implementou os Self-Organizing Maps em software. Os resultados foram similares e o circuito proposto atingiu uma acurácia de 94,53%.

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SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing

Cited by 23 publications

References 43 publications

Video Chunk Processor: Low-Latency Parallel Processing of 3 x 3-pixel Image Kernels

Video Chunk Processor: Low-Latency Parallel Processing of 3 x 3-pixel Image Kernels

A Data Collection Strategy for Heterogeneous Wireless Sensor Networks Based on Energy Efficiency and Collaborative Optimization

Previsão de surtos epiléticos usando Mapas Auto Organizáveis executados diretamente em hardware

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