The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware-based imaging systems arises. These fully hardware systems solve the fundamental problem inherent in software-based solutions, in which the speed of the algorithms depend on the instruction cycle speed of the processor. Once an algorithm is designed directly on hardware, the speed of the algorithm depends on the system clock frequency and the propagation delays of the logic cells (or standard cells) used in the design, usually measured in nanoseconds per cell. Therefore, such systems no longer depend on any instruction cycle delays, as there is no microprocessor involved. Most modern imaging and communications systems rely on digital signal processing (DSP) to compute complex mathematical operations. The emergence of powerful and low-cost field-programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled the development of many such DSP hardware applications, traditionally implemented only as software solutions.
Video framebuffers are usually used in video processing systems to store an entire frame of video data required for processing. These framebuffers make extensive use of random access memory (RAM) technologies and interfaces that use them. Recent trends in the high-speed video discuss the use of higher speed memory interfaces such as DDR4 (double-datarate 4) and HBM (high-bandwidth memory) interfaces. To meet the demand for higher image resolutions and frame rates, larger and faster framebuffer memories are required. While it is not feasible for software to read and process parts of an image quickly and efficiently enough due to the high speed of the incoming video, a hardware-based video processing solution poses no such limitation. Existing discussions involve the use of framebuffers even in hardware-based implementations, which greatly reduces the speed and efficiency of such implementations. This paper introduces hardware techniques to read and process kernels without the need to store the entire image frame. This reduces the memory requirements significantly without losing the quality of the processed images.
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