Some experimental results on placement techniques

Hanan, M.; Wolff, P. K.; Agule, B. J.

doi:10.1145/62882.62888

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…88 Force-directed placement algorithms can obtain fairly non-overlapping placements on circuit boards without the use of additional means of optimisation 89 and, as such, have proven popular in applications to VLSI circuit boards since the 1960s. 90–96…”

Section: Applications Of Force-directed Algorithmsmentioning

confidence: 99%

Force-directed algorithms for schematic drawings and placement: A survey

Cheong

2019

Information Visualization

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Force-directed algorithms have been developed over the last 50 years and used in many application fields, including information visualisation, biological network visualisation, sensor networks, routing algorithms, scheduling, and graph drawing. Our survey provides a comprehensive summary of developments and a full roadmap for state-of-the-art force-directed algorithms in schematic drawings and placement. We classified the model of force-directed algorithms into classical and hybrid. The classical force-directed algorithms are further classified as follows: (a) accumulated force models, (b) energy function minimisation models and (c) combinatorial optimisation models. The hybrid force-directed algorithms are classified as follows: (a) parallel and hardware accelerated models, (b) multilevel force-directed models and (c) multidimensional scaling force-directed algorithms. Five categories of application domains in which force-directed algorithms have been adopted for schematic drawings and placement are also summarised: (a) aesthetic drawings for general networks, (b) component placement and scheduling in high-level synthesis of very-large-scale integration circuits design, (c) information visualisation, (d) biological network visualisation and (e) node placement and localisation for sensor networks.

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Section: Applications Of Force-directed Algorithmsmentioning

confidence: 99%

Force-directed algorithms for schematic drawings and placement: A survey

Cheong

2019

Information Visualization

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“…The placement algorithm used in LLAMA is based on the force-directed placement technique [10]. But here, the forces on the nets (used to determine the relative positions of cells in the placement) are proportional to the net-weights.…”

Section: Usage Of Net-weights During Layoutmentioning

confidence: 99%

Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed‐Efficient Circuits

Chandrasekhar¹,

McCharles²,

Wallace

1997

VLSI Design

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Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit area and delay during layout. An algorithm for computing logic equivalence classes and performing net swapping using the equivalence classes during layout is described. Lastly, it shows the sensitivity of post-layout delays of circuits to wiring models used in synthesis and demonstrates how resynthesis techniques can be effectively used to generate good post-layout implementation. Significant reductions in post-layout area and delay on several industrial designs have been observed.

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“…For this example, let the x and y coordinates consist of three bits, n s = ny = 3 and n o = 0. The first row of ~ has all six detectors defined, and it gives the x, y coordinates for cell 1 as (2,5). This is shown by the single shaded square in Fig.…”

Section: Theoretical Aspects Of Gampmentioning

confidence: 99%

“…Many heuristic strategies for macro cell placement based on iterative improvement have been reported recently. Examples are force-directed placement [1,2,28], rain-cut placement [3,4,29], simulated annealing [5][6][7], and passive resistive optimization [8]. Simulated annealing is one of the latest techniques being used for cell placement.…”

Section: Introductionmentioning

confidence: 99%

Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

1991

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The genetic algorithm has been applied to the VLSI module placement problem. This algorithm is an iterative, evolutional approach. A placement configuration is represented by a set of primitive features such as location and orientation, and the features are arranged in the form of a two-dimensional bitmap chromosome. The representation is flexible, and can handle arbitrarily shaped cells, and pads, and is applicable to the placement of macro cells, and gate arrays. Three new versions of genetic operators, namely, crossover, inversion and mutation, are used to explore the solution space. Crossover creates new configurations by combining attributes from a pair of existing configurations. This feature passing scheme constitutes the primary difference between our genetic approach and the other traditional searching techniques. Inversion enables more uniform inheritance of features from one generation to the next, and mutation prevents the algorithm from getting trapped at local optima. We have pointed out that the bitmap representation enables the algorithm to divide the entire solution space into a set of feature-equivalent classes, or schemata where each class contains a set of solutions with common physical attributes. We show that the genetic algorithm adaptively biases the search based on the past observed fitness of the schemata. We also demonstrated the power of the genetic algorithm experimentally for macro cell placement, and obtained satisfactory results.

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Some experimental results on placement techniques

Cited by 3 publications

References 3 publications

Force-directed algorithms for schematic drawings and placement: A survey

Force-directed algorithms for schematic drawings and placement: A survey

Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed‐Efficient Circuits

Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

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