Solderless assembly of electronic products &amp;#x2014; a more reliable and more cost effective approach to electronics manufacturing?

Fjelstad, Joseph

doi:10.1109/vppc.2009.5289876

Cited by 3 publications

(3 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, classical wire bonding was used, reducing the lead length to a few 100µm. Bonding can be replaced by sequential build up technologies, implementing direct copper interconnects from the ASIC pad to the piezo material metallization [16]. In this way, the interconnect length can be reduced to less than 100µm.…”

Section: A Transducer Excitationmentioning

confidence: 99%

Concepts and architecture for a thumb-sized smart IoT ultrasound measurement system

Delsing

Deventer

Eliasson

et al. 2016

2016 IEEE International Ultrasonics Symposium (IUS)

View full text Add to dashboard Cite

Abstract-This paper presents the technology concepts for a "thumb"-sized self-contained ultrasonic IoT measurement system. An overall architecture is proposed, and key elements are discussed with solutions using existing technology, thus arguing that realization is possible with the current technology.Such an ultrasonic IoT measurement system is constrained by its size and available energy, although it requires at least decent computational and communication resources. Because streaming data from such a device is not advisable from an energy viewpoint, there is a need for resource efficient (energy, memory and computational power) data analysis.An architecture with the following parts as well as some implementation details and performance data are proposed here:• Energy supply, battery and super capacitor • Transducer excitation achieving almost zero electrical losses • Event detection sensor interface • Data aggregation using sparse approximation and learned feature dictionaries, adapted to resource constrained embedded systems • IoT communication protocols and implementations enabling event -based communication and System of Systems integration capabilities The optimization of system level performance requires each subsystem to be optimized for the specific measurement situation taking into account the subsystem interdependencies. This can be performed using a combined electrical and acoustical model of the system. Here, the model allowing electronic and acoustic co-simulation using SPICE is an important tool bridging the electronic and acoustic domains.

show abstract

Section: A Transducer Excitationmentioning

confidence: 99%

Concepts and architecture for a thumb-sized smart IoT ultrasound measurement system

Delsing

Deventer

Eliasson

et al. 2016

2016 IEEE International Ultrasonics Symposium (IUS)

View full text Add to dashboard Cite

show abstract

“…• Extensions L 1 and L 2 have been selected as one of the following pairs: (0.1, 0.1), (5,5) and (15,15) mm.…”

Section: Peec Simulationsmentioning

confidence: 99%

“…SBU processes offer several advantages in terms of manufacturing cost, performance, product size and short-/long-term reliability, and these advantages have been thoroughly discussed in [5], [4], [6]. Generally, manufacturing cost scales with size and production volume, the economic advantage of reducing board size by embedding passive components has been demonstrated in [9].…”

Section: Introductionmentioning

confidence: 99%

Contactless Testing of Circuit Interconnects

Renbi

Delsing

2015

J Electron Test

View full text Add to dashboard Cite

State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

show abstract