Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines

Kim, Jeremie; Patel, Minesh; Hassan, Hasan; Mutlu, Onur

doi:10.1109/iccd.2018.00051

Cited by 53 publications

(92 citation statements)

References 42 publications

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“…We profile the DRAM 1) before running DNN inference, and 2) when the environmental factors that can affect the error patterns change (e.g., when temperature changes). We find that an error model can be accurate for many days if the environmental conditions do not change significantly, as also observed in prior work [76,93,94].…”

Section: Accuracy Validation Of the Error Modelssupporting

confidence: 87%

“…In our experiments with real DRAM modules, we find that the errors are temporally consistent and stable for days of continuous execution (with ±5°C deviations from the profiling temperature), without requiring re-characterization. Prior works [76,94] report similar results.…”

Section: Enabling Eden With Error Modelssupporting

confidence: 68%

“…We model this error distribution with two key parameters: 1) P B is the percentage of weak cells in bitline B, and 2) F B is the probability of an error in the weak cells of bitline B. Vendor C Figure 5: Bit error rates depend on the data pattern stored in DRAM, with reduced supply voltage [21] and reduced t RC D [19,21,76,93,94], motivating Error Model 3. Data is based on DDR3 DRAM modules from three major vendors.…”

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

“…• Error Model 2: the bit errors follow a horizontal distribution across the wordlines of a DRAM bank. Prior works [19,21,76,93] observe that some DRAM rows experience more bit flips than others under reduced DRAM parameters due to 1) manufacturing process variation across DRAM rows [19,21,76], and 2) design-induced latency variation that arises from the varying distance between different DRAM rows and the row buffer [93]. We model this error distribution with two key parameters: 1) P W is the percentage of weak cells in wordline W , and 2) F W is the probability of an error in the weak cells of wordline W .…”

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

See 3 more Smart Citations

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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The effectiveness of deep neural networks (DNN) in vision, speech, and language processing has prompted a tremendous demand for energy-efficient high-performance DNN inference systems. Due to the increasing memory intensity of most DNN workloads, main memory can dominate the system's energy consumption and stall time. One effective way to reduce the energy consumption and increase the performance of DNN inference systems is by using approximate memory, which operates with reduced supply voltage and reduced access latency parameters that violate standard specifications. Using approximate memory reduces reliability, leading to higher bit error rates. Fortunately, neural networks have an intrinsic capacity to tolerate increased bit errors. This can enable energy-efficient and high-performance neural network inference using approximate DRAM devices.Based on this observation, we propose EDEN, the first general framework that reduces DNN energy consumption and DNN evaluation latency by using approximate DRAM devices, while strictly meeting a user-specified target DNN accuracy. EDEN relies on two key ideas: 1) retraining the DNN for a target approximate DRAM device to increase the DNN's error tolerance, and 2) efficient mapping of the error tolerance of each individual DNN data type to a corresponding approximate DRAM partition in a way that meets the user-specified DNN accuracy requirements.We evaluate EDEN on multi-core CPUs, GPUs, and DNN accelerators with error models obtained from real approximate DRAM devices. We show that EDEN's DNN retraining technique reliably improves the error resiliency of the DNN by an order of magnitude. For a target accuracy within 1% of the original DNN, our results show that EDEN enables 1) an average DRAM energy reduction of 21%, 37%, 31%, and 32% in CPU, GPU, and two different DNN accelerator architectures, respectively, across a variety of state-ofthe-art networks, and 2) an average (maximum) speedup of 8% (17%) and 2.7% (5.5%) in CPU and GPU architectures, respectively, when evaluating latency-bound neural networks.

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Section: Accuracy Validation Of the Error Modelssupporting

confidence: 87%

Section: Enabling Eden With Error Modelssupporting

confidence: 68%

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

See 2 more Smart Citations

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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show abstract

“…For example, the timing slack in the specified precharge timing parameter or the refresh latency parameter can be exploited by the DRAM chip itself to internally issue refresh operations to targeted rows with some probability. Even though such timing slack exists in DRAM chips, as shown by many recent experimental studies [57,69,125,147,151], we do not believe this is a robust solution since 1) the timing slack may not exist under all operating conditions or for all chips, 2) many studies would like to reduce the timing slack as much as possible to improve DRAM performance and energy [57,69,125,147,151]. asynchronous with the processor, a simple controller that is tightly coupled with the memory chip can freely and easily implement PARA internally to the memory chip.…”

Section: Modulementioning

confidence: 99%

RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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154

129

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This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference [133]. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology.Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this article, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or Phase Change Memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

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RowHammer and Beyond

Mutlu

2019

Constructive Side-Channel Analysis and Secure Design

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We will discuss the RowHammer problem in DRAM, which is a prime (and likely the first) example of how a circuit-level failure mechanism in Dynamic Random Access Memory (DRAM) can cause a practical and widespread system security vulnerability. RowHammer is the phenomenon that repeatedly accessing a row in a modern DRAM chip predictably causes errors in physically-adjacent rows. It is caused by a hardware failure mechanism called read disturb errors. Building on our initial fundamental work that appeared at ISCA 2014, Google Project Zero demonstrated that this hardware phenomenon can be exploited by user-level programs to gain kernel privileges. Many other recent works demonstrated other attacks exploiting RowHammer, including remote takeover of a server vulnerable to RowHammer. We will analyze the root causes of the problem and examine solution directions. We will also discuss what other problems may be lurking in DRAM and other types of memories, e.g., NAND flash and Phase Change Memory, which can potentially threaten the foundations of reliable and secure systems, as the memory technologies scale to higher densities.

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Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines

Cited by 53 publications

References 42 publications

Eden

Eden

RowHammer: A Retrospective

RowHammer and Beyond

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