Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Abstract

This work demonstrates an ultra-low power, software-defined wireless transceiver designed for IoT applications using an open-source 32-bit RISC-V core. The key driver behind this success is an optimized hardware/software partitioning of the receiver's digital signal processing operators. We benchmarked our architecture on an algorithm for the detection of FSK-modulated frames using a RISC-V compatible core and ARM Cortex-M series processors. We use only standard compilation tools and no assembly-level optimizations. Our results show that Bluetooth LE frames can be detected with an estimated peak core power consumption of 1.6 mW on a 28 nm FDSOI technology, and falling to less than 0.6 mW (on average) during symbol demodulation. This is achieved at nominal voltage. Compared to state of the art, our work offers a power efficient alternative to the design of dedicated baseband processors for ultra-low power software-defined radios with a low software complexity.

A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

“…This excludes the reuse of widely available software tool chains and DSP libraries. An alternative approach was proposed in our previous work [9] with a strategy based on small general purpose micro-architectures (including RISC-V). Thanks to advanced CMOS scaling and sufficiently high clocks, we showed that a timing and power consumption performance compatible with ULP IoT protocols can be achieved on these platforms, even without voltage scaling.…”

“…The number of additional instructions is intentionally limited in order to minimize the impact on the core's power consumption (only +9% overhead with respect to the base RISC-V design.) As discussed at length in our previous work [9], the vectorial hardware extensions proposed are of limited interest for complex (versus real) data and the proposed hardware loop mechanism can rarely be used in our algorithms which typically contain conditional branches. However, for completeness, we included comparative results using this architecture in Tables 3 and 5.…”

“…We propose an instruction set extension for the RISC-V ISA tailored to the needs of wireless DSP and that Fig. 1: Simplified architecture of software-defined RF receiver (reproduced from [9]) achieves high cycle count reductions with 'near zero' power overhead;…”

Low Complexity LoRa Frame Synchronization for Ultra-Low Power Software-Defined Radios

“…To study the impact of CF O f rac estimation precision in various Eb/N o conditions, infinite precision Monte-Carlo simulations are run in which frame synchronization is performed assuming frames affected by a CF O randomly chosen in the range of ±34 ppm. CF O f rac estimation is performed on the preamble symbols using the method described in Section II-E. For comparison, Figure 10 also shows the accuracy of the CF O f rac estimation method proposed in [16], equation (9). We see that, not only does this last algorithm perform less accurately at low Eb/N o, the algorithm itself requires 2 SF additional complex multiplications and sums per symbol employed.…”

“…Another motivation for gaining a better understanding of the LoRa physical layer is the development of LoRa-compatible demodulation software for recently proposed ultra-low power software defined radios (ULP-SDR) [7][8] [9]. Indeed, compared to today's commodity IoT transceivers which are mostly implemented in hardware, software-based wireless transceivers enable the implementation of different physical layers on the same hardware.…”