SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

Hassan, Hasan; Vijaykumar, Nandita; Khan, Samira; Ghose, Saugata; Chang, Ki-Ho; Pekhimenko, Gennady; Lee, Donghyuk; Ergin, Oğuz; Mutlu, Onur

doi:10.1109/hpca.2017.62

Cited by 110 publications

(167 citation statements)

References 61 publications

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“…In order to test our hypothesis that DRAM cells are an effective source of entropy when accessed with reduced DRAM timing parameters, we developed an infrastructure to characterize modern LPDDR4 DRAM chips. We also use an infrastructure for DDR3 DRAM chips, SoftMC [52,132], to demonstrate empirically that our proposal is applicable beyond the LPDDR4 technology. Both testing environments give us precise control over DRAM commands and DRAM timing parameters as veri ed with a logic analyzer probing the command bus.…”

Section: Testing Environmentmentioning

confidence: 99%

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

Kim

Patel

Hassan

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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105

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We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source.The key idea is to intentionally violate the DRAM access timing parameters and use the resulting errors as the source of randomness. Our technique speci cally decreases the DRAM row activation latency (timing parameter t RCD ) below manufacturerrecommended speci cations, to induce read errors, or activation failures, that exhibit true random behavior. We then aggregate the resulting data from multiple cells to obtain a TRNG capable of providing a high throughput of random numbers at low latency.To demonstrate that our TRNG design is viable using commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verify our observations using four additional DDR3 DRAM devices from the same manufacturers. Our results show that many cells in each device produce random data that remains robust over both time and temperature variation. We use our observations to develop D-RaNGe, a methodology for extracting true random numbers from commodity DRAM devices with high throughput and low latency by deliberately violating the read access timing parameters. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and nd that D-RaNGe: 1) successfully passes each test, and 2) generates true random numbers with over two orders of magnitude higher throughput than the previous highest-throughput DRAM-based TRNG.

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Section: Testing Environmentmentioning

confidence: 99%

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

Kim

Patel

Hassan

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Self Cite

105

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“…Specifically, when a DRAM row is opened (i.e., activated) and closed (i.e., precharged) repeatedly (i.e., hammered), enough times within a DRAM refresh interval, one or more bits in physically-adjacent DRAM rows can be flipped to the wrong value. Using an FPGA-based DRAM testing infrastructure [70,42], we tested 129 DRAM modules manufactured by three major manufacturers in seven recent years (2008)(2009)(2010)(2011)(2012)(2013)(2014) and found that 110 of them exhibited RowHammer errors, the earliest of which dates back to 2010. Our ISCA 2014 paper [55] provides a detailed and rigorous analysis of various characteristics of RowHammer, including its data pattern dependence, repeatability of errors, relationship with leaky cells, and various circuit-level causes of the phenomenon.…”

Section: Discussionmentioning

confidence: 99%

RowHammer and Beyond

Mutlu

2019

Constructive Side-Channel Analysis and Secure Design

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We will discuss the RowHammer problem in DRAM, which is a prime (and likely the first) example of how a circuit-level failure mechanism in Dynamic Random Access Memory (DRAM) can cause a practical and widespread system security vulnerability. RowHammer is the phenomenon that repeatedly accessing a row in a modern DRAM chip predictably causes errors in physically-adjacent rows. It is caused by a hardware failure mechanism called read disturb errors. Building on our initial fundamental work that appeared at ISCA 2014, Google Project Zero demonstrated that this hardware phenomenon can be exploited by user-level programs to gain kernel privileges. Many other recent works demonstrated other attacks exploiting RowHammer, including remote takeover of a server vulnerable to RowHammer. We will analyze the root causes of the problem and examine solution directions. We will also discuss what other problems may be lurking in DRAM and other types of memories, e.g., NAND flash and Phase Change Memory, which can potentially threaten the foundations of reliable and secure systems, as the memory technologies scale to higher densities.

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“…The DRAM cell characteristics at the reduced t RP mostly rely on the internal structure of a DRAM module, process variations, layout variations, data dependency, etc. [20], [27], [37], [46], [49], [51]- [53]. Fig.…”

Section: A Precharge Latency and Source Of Variationsmentioning

confidence: 99%

“…if is_pattern_independent(temp) == true then 8: goldenDataLoc (R (i) , k, β (i, j)) = true; 9: goldenData (R (i) , k, β (i, j)) = temp; Our results are based on experiments conducted with six memory banks from two commercial DDR3 memory modules of two major memory vendors 2 (namely A and B). We used SoftMC (Soft Memory Controller [51]) along with the Xilinx ML605 Evaluation Kit which is embedded with Virtex-6 FPGA. SoftMC uses Riffa [66] framework to establish communication between a host PC and the evaluation board through x8 PCIe bus.…”

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confidence: 99%

PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures

et al. 2019

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Physically Unclonable Functions (PUFs) are potential security blocks to generate unique and more secure keys in low-cost cryptographic applications. Dynamic random-access memory (DRAM) has been proposed as one of the promising candidates for generating robust keys. Unfortunately, the existing techniques of generating device signatures from DRAM is very slow, destructive (destroy the current data), and disruptive to system operation. In this paper, we propose precharge latency-based PUF (PreLatPUF) that exploits DRAM precharge latency variations to generate signatures. The proposed PreLatPUF is fast, robust, least disruptive, and non-destructive. The silicon results from commercially available DDR3 chips from different manufacturers show that the proposed key generation technique is at least ∼ 1, 192X faster than the existing approaches, while reliably reproducing the key in extreme operating conditions. INDEX TERMS DRAM-PUF, DRAM latency-based PUF, robust key generation.

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SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

Cited by 110 publications

References 61 publications

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

RowHammer and Beyond

PreLatPUF: Exploiting DRAM Latency Variations for Generating Robust Device Signatures

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