Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Mesa-Martinez, Francisco J.; Renau, Jose

doi:10.1109/micro.2007.13

Cited by 133 publications

(59 citation statements)

References 11 publications

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“…1.2 were computed by taking the performance metric R max 6 values for the top 10 systems in each year from the TOP500, averaging them at each year (to get an overall technology trend), and then computing the CAGR over a 3 year period, and adjusting back to 1 year factors. 7 The transition in the year 2004 is clearly visible in these metrics. During this entire period, the R max performance metric averaged about 1.8, meaning the system performance went up by a factor of 1.8 each year.…”

Section: Seeing the "Perfect Storm" In Metric Changesmentioning

confidence: 96%

“…Black et al [1] studied two forms of die stacking: placing cache chips on top of a conventional microprocessor, and splitting such a microprocessor into two die. Ghosh and Lee [7] and Kgil et al [13] studied microarchitectures that use 3D stacking to reduce energy costs. Loh [18] discussed re-architecting DRAM die that would stack above a conventional processor core in ways that increase the bandwidth and memory level parallelism of the memory as seen by the processor.…”

Section: Emerging 3d Architecturesmentioning

confidence: 99%

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Yearly update : exascale projections for 2013.

Kogge

Resnick²

2013

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The HPC architectures of today are significantly different for a decade ago, with high odds that further changes will occur on the road to Exascale. This paper discusses the "perfect storm" in technology that produced this change, the classes of architectures we are dealing with, and probable trends in how they will evolve. These properties and trends are then evaluated in terms of what it likely means to future Exascale systems and applications. 3This page intentionally left blank.

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Section: Seeing the "Perfect Storm" In Metric Changesmentioning

confidence: 96%

Section: Emerging 3d Architecturesmentioning

confidence: 99%

Yearly update : exascale projections for 2013.

Kogge

Resnick²

2013

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“…Ghosh et al [10] propose SmartRefresh, which reduces refresh power in DRAMs by adding timeout counters per line. This avoids unnecessary refreshes of lines that were recently accessed.…”

Section: Related Workmentioning

confidence: 99%

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Agrawal

Ansari

Torrellas

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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EDRAM cells require periodic refresh, which ends up consuming substantial energy for large last-level caches. In practice, it is well known that different eDRAM cells can exhibit very different charge-retention properties. Unfortunately, current systems pessimistically assume worst-case retention times, and end up refreshing all the cells at a conservatively-high rate. In this paper, we propose an alternative approach. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. The model shows that the retention times of cells in large eDRAM modules exhibit spatial correlation. Therefore, we logically divide the eDRAM module into regions or tiles, profile the retention properties of each tile, and program their refresh requirements in small counters in the cache controller. With this architecture, also called Mosaic, we refresh each tile at a different rate. The result is a 20x reduction in the number of refreshes in large eDRAM modules -practically eliminating refresh as a source of energy consumption.

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“…RELATED WORK Past work on DRAM refresh focuses on hardware principles, such as refresh methods (mostly in patents), power enhancements, fault tolerance support or discharge monitoring [3]- [7], [17], [22]. One exception is the work by Moshnyaga et al that utilizes operating system facilities to trade off DRAM vs. flash storage to mitigate current differences in access latencies, bandwidth and power consumption [13].…”

Section: Reduction In Dram Energy Consumptionmentioning

confidence: 99%

Making DRAM refresh predictable

Bhat

Mueller

2011

Real-Time Syst

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Abstract-Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known. While periods are generally derived from the problem specification, a task's code needs to be statically analyzed to derive safe and tight bounds on its WCET. Such static timing analysis abstracts from program input and considers loop bounds and architectural features, such as pipelining and caching. However, unpredictability due to dynamic memory (DRAM) refresh cannot be accounted for by such analysis, which limits its applicability to systems with static memory (SRAM).In this paper, we assess the impact of DRAM refresh on task execution times and demonstrate how predictability is adversely affected leading to unsafe hard real-time system design. We subsequently contribute a novel and effective approach to overcome this problem through software-initiated DRAM refresh. We develop (1) a pure software and (2) a hybrid hardware/software refresh scheme. Both schemes provide predictable timings and fully replace the classical hardware autorefresh. We discuss implementation details based on this design for multiple concrete embedded platforms and experimentally assess the benefits of different schemes on these platforms. The resulting predictable execution behavior in the presence of DRAM refresh combined with the additional benefit of reduced access delays is unprecedented, to the best of our knowledge.

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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Cited by 133 publications

References 11 publications

Yearly update : exascale projections for 2013.

Yearly update : exascale projections for 2013.

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

Making DRAM refresh predictable

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