Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation

Urban, Christoph; Emam, Mostafa; Sandow, C.; Zhao, Qing‐Tai; Fox, A.; Mantl, S.; Raskin, Jean‐Pierre

doi:10.1016/j.sse.2010.04.013

Cited by 11 publications

(8 citation statements)

References 29 publications

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“…6(a)]. The C gs capacitance increases both with L dop and N dop (agreeing with the experimentally observed augmentation in [19]) due to the larger accumulation of carriers in the DS layer area located between source and gate terminals, and so the increase in carrier concentration is locally enhanced as a response of a gate voltage step.…”

Section: Resultssupporting

confidence: 82%

“…Several authors have disclosed the advantages of DS layers, focusing on the reduced effective barrier height, the I -V curves, the parasitic contact resistance, the ON-OFF current ratio or the variation of the threshold voltage [6], [8], [12], [14]- [23] proving that the use of DS layers provides higher performance SB-MOSFETs for several analog and digital applications. However, few studies address the effects of the presence of a DS layer on the transconductance or cutoff frequency of SB-MOSFETs [17], [19], [24], [25]. The aim of this paper is to provide an in-depth analysis of the optimization of the DS layer characteristics in an n-type SB-MOSFET by means of ensemble Monte Carlo (EMC) simulation.…”

Section: Introductionmentioning

confidence: 99%

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Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

Martín

Couso

Pascual

et al. 2014

IEEE Trans. Electron Devices

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This paper presents a detailed Monte Carlo study of the optimization of the dopant segregation (DS) layer in n-type Schottky barrier (SB)-MOSFET. It is shown that with a careful control of the DS layer parameters, dopant concentration (N dop ), and length (L dop ), the performance of the devices is significantly enhanced. The presence of the DS layer induces crucial effects in the injection processes at the Schottky contacts. The benefits of increasing the length and the doping level of the DS layer are studied from the microscopic point of view (transit times, average number of scatterings). The effect of varying these parameters is also analyzed through the nonquasi-static parameters of the small signal equivalent circuit, which can be useful for designers to improve the reliability of the SB-MOSFET technology. Index Terms-Dopant segregation (DS), Monte Carlo methods, RF performance, Schottky barrier (SB)-MOSFETs.

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Section: Resultssupporting

confidence: 82%

Section: Introductionmentioning

confidence: 99%

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

Martín

Couso

Pascual

et al. 2014

IEEE Trans. Electron Devices

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“…Recently, Urban et al have demonstrated the fabrication of high performance Schottky barrier MOSFETs for CMOS applications using an alternative method of ohmic contact formation based on Nickel silicidation with dopant segregation (DS) [4]- [7]. In such a process, dopants are expected to be "snow-plowed" by the growing silicide and consequently to accumulate at the silicide/Silicon interface.…”

Section: Introductionmentioning

confidence: 99%

“…DS occurs provided that the solid solubility of the dopant is lower than that on Silicon and that the intrinsic diffusion of the dopant is significantly low at the silicidation temperature and also there are point defects at the silicide/Silicon interface [8]- [10]. So far, n and p-type Ohmic contacts were successfully formed using Nickel silicidation with dopant segregation [7]. Moreover, it has been demonstrated that the contact resistance of layers with low interface roughness, can be significantly reduced [11].…”

Section: Introductionmentioning

confidence: 99%

Formation of Insulated-Gate Bipolar Transistor Highly Activated Anodes via Nickel Silicidation With Dopant Segregation

Minamisawa

Papadopoulos

Jabrany

et al. 2015

IEEE Electron Device Lett.

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We propose a low-temperature nickel silicidation with a dopant segregation approach to form shallow anode profiles in thin wafer insulated-gate bipolar transistors (IGBTs). The process provides an anode with a boron peak concentration of 3 × 10 19 /cm 3 after annealing at 400°C. The silicidation results in a NiSi phase with a strong interface roughness, independent of the polishing process after grinding. The devices exhibit characteristics comparable with the state-of-the-art IGBTs in terms of voltage drop (V CE,ON ), which indicates that a higher anode activation was achieved at low temperature in comparison with the reference samples, since the anode is <27% of its initial thickness. Devices that underwent chemical mechanical planarization exhibit higher V CE,ON than those without, possibly due the increase of surface roughness.

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“…In spite of having improved drive current due to DSL, the high frequency performance of DSSB SOI MOSFET deteriorates as compared to RSD UTB [6,8]. In order to improve the high frequency performance of this device lot of work has been carried out by different groups through experiments [9][10] and by simulations [11][12]. However, the impact of segregation layer doping density (N DSL ) and the length (L DSL ) on scalability and analog/RF performance of this device in sub-30 nm regime has not been investigated.…”

Section: Introductionmentioning

confidence: 99%

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

Patil

Qureshi²

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, the impact of segregation layer density (N DSL ) and length (L DSL ) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the N DSL the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the L DSL the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a commonsource amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing N DSL and L DSL of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits

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Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation

Cited by 11 publications

References 29 publications

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

Formation of Insulated-Gate Bipolar Transistor Highly Activated Anodes via Nickel Silicidation With Dopant Segregation

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

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