Small- and Large-Signal Performance Up To 175 °C of Low-Cost Porous Silicon Substrate for RF Applications

Rack, Martin; Belaroussi, Y.; Ali, Khaled Ben; Scheen, Gilles; Esfeh, Babak Kazemi; Raskin, Jean‐Pierre

doi:10.1109/ted.2018.2818466

Cited by 21 publications

(12 citation statements)

References 38 publications

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“…It must be mentioned that the effect of temperature on transmission line loss is well recognized in bulk silicon RF technology and potential alternatives such as silicon-oninsulator, porous and trap-rich Si substrates have been shown to exhibit a higher tolerance to temperature effects. [13][14][15][16][17] However, the integration of GaN with these alternative substrates is hardly straightforward in view of the challenges in epitaxy and processing, to say nothing of potential thermal management considerations.…”

Section: Mmicmentioning

confidence: 99%

Quantifying Temperature-Dependent Substrate Loss in GaN-on-Si RF Technology

Chandrasekar

Uren

Casbon

et al. 2019

IEEE Trans. Electron Devices

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Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperaturedependent CPW line loss at various operating frequency bands are then presented. CPW lines for GaN-on-high resistivity Si are shown to have a pronounced temperature-dependence for temperatures above 150°C and have lower substrate losses for frequencies above the X-band. On the other hand, GaN-on-low resistivity Si is shown to be more temperature-insensitive and have lower substrate losses than even HR-Si for lower operating frequencies. The effect of various CPW geometries on substrate loss is also presented to generalize the discussion. These results are expected to act as a benchmark for temperature dependent substrate loss in GaN-on-Si RF technology.

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Section: Mmicmentioning

confidence: 99%

Quantifying Temperature-Dependent Substrate Loss in GaN-on-Si RF Technology

Chandrasekar

Uren

Casbon

et al. 2019

IEEE Trans. Electron Devices

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“…From AFM image ( Figure 3A), a change in the PSi structure is observed, and for a PSi-S substrate (1-10 ΩÁcm), the size of pores T A B L E 1 Comparison between two nominal resistivity According to Figure 3C, when the roughness is close to value of 1, this indicates a smooth surface. 13,14 From this result, we can con- Concerning the electrical properties of PSi, they were investigated in Rack et al, 21 where the evaluated performances are summa-…”

Section: Resultsmentioning

confidence: 85%

“…Contrary to our previous papers where we have focused on substrate electrical performances, [19][20][21]…”

Section: Introductionmentioning

confidence: 80%

“…Concerning the electrical properties of PSi, they were investigated in Rack et al, 21 where the evaluated performances are summarized and highlighted the merits of PSi and, in particular, the PSi‐S substrate. The latter provides the highest RF electrical performances, with very strong linearity, low relative effective permittivity (3.5), and high effective resistivity (5 kΩ·cm), it maintains its high performance all the way up to 175°C.…”

Section: Resultsmentioning

confidence: 99%

“…Contrary to our previous papers where we have focused on substrate electrical performances, 19–21 in this article, we figure out the structural and mechanical properties of PSi substrates, these characterizations are undertaken with the aim of better adapting the porosification parameters in the idea of integrating the PSi with the standard processes of the industry. So we have investigated the nanomechanical properties and the structure analysis of the PSi layer with different thicknesses formed on p‐type Si substrate with two resistivities.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Structural and nanomechanical properties of porous silicon: Cheap substrate for CMOS process industry

Belaroussi

Scheen

Saadi³

et al. 2020

Surface & Interface Analysis

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The surface topology of porous silicon (PSi) is a relevant parameter that decides the compatibility of such substrate with CMOS process. Using standard resistivity (1–10 Ω·cm) of Si substrate to fabricate PSi‐S is a low cost solution for the industry. In this paper, through an atomic force microscopy (AFM) analysis, the root mean square (RMS) roughness, the power spectral density and the correlation length were determined for different PSi layers. Furthermore, the measured hardness, Young's modulus, and stress have been made for different thicknesses of PSi: 5, 10, 50, and 200 μm. The obtained results demonstrated that very interesting properties have been achieved with the 50 μm‐thick PSi‐S layer with a maximum porosity around 65%, a surface roughness less than 1 nm and a hardness value of (~1 GPa). The realized results encourage the utilization the PSi‐based substrate into the industry process and thus the development of a Systems‐on‐Chip (SoC).

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