Sizing of MOS transistors for amplifier design

Pinto, Rosanna; Schneider, M.C.; Montoro, C.G.

doi:10.1109/iscas.2000.858719

Cited by 8 publications

(5 citation statements)

References 3 publications

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“…15 This area is the area of the high-end DDS. 16 In the area of high-end DDS, all the choices made in this paper can be not more valid and a better solution has to be found for power optimization. To 14 Getting a high DR from an analog block can cause a sensible increase in the power consumption.…”

Section: Resultsmentioning

confidence: 98%

“…Its size depends only on the required resolution and reference clock frequency. 16 The DAC required number of bits in this area is above 12. Therefore, to still keep the same DAC topology, a laser trimming of the resistances or a calibration loop are required.…”

Section: Resultsmentioning

confidence: 99%

“…9 Following the work in [13], the ROM power consumption can be evaluated by considering all the different components involved in a single phase to amplitude conversion. The power consumed by the memory cells on a row during one precharge or evaluation can be approximated by the following: (16) where is the approximated power consumption of the ROM, is the capacitance of a unit wirelength with minimum width, is the minimum-size gate capacitance, is the power-supply voltage, and is the voltage swing of each memory cell. Defining the memory cell as square, then the column interconnection length of the memory matrix is .…”

Section: B Phase-accumulator and Rom Power-consumption Estimationsmentioning

confidence: 99%

“…To reduce the current consumption, it is reasonable to drive the transistors in weak inversion. Given the required voltage gain , the minimum channel length to achieve this gain with a single-stage amplifier is given by the following [16]: (26) where is the thermal voltage roughly equal to 25 mV, is the slope factor ( in weak inversion), is the Early voltage, and is the inversion coefficient (between 0.1 and 1 in weak inversion). Considering an inversion coefficient equal to 0.5, the required transistor channel length for a gain of 100 is equal to 1.62 m. Now, the relation between current and gate-source voltage in a MOS transistor is given by the following relation: (27) where is the electron mobility, is the gate capacitance per unit area, is the transistor width, is the channel length, and is the overdrive voltage.…”

Section: ) R-2r Dacmentioning

confidence: 99%

“…The minimum bias current to achieve the required specifications is given by the following [16]: (31) where GB is the gain-bandwidth product and is the load capacitance. The buffer-estimated power consumption for the three different frequencies is given in Table X.…”

Section: ) R-2r Dacmentioning

confidence: 99%

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Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

Lopelli

Tang²,

Roermund

2009

IEEE Trans. Circuits Syst. I

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Abstract-The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation.Index Terms-Direct digital synthesizer (DDS), frequency hopping (FH), low power, power estimation, sensor networks.

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Section: Resultsmentioning

confidence: 98%

Section: Resultsmentioning

confidence: 99%

Section: B Phase-accumulator and Rom Power-consumption Estimationsmentioning

confidence: 99%

Section: ) R-2r Dacmentioning

confidence: 99%

Section: ) R-2r Dacmentioning

confidence: 99%

See 3 more Smart Citations

Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

Lopelli

Tang²,

Roermund

2009

IEEE Trans. Circuits Syst. I

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FHSS Systems: State-of-the-Art and Power Trade-offs

Lopelli¹,

Tang

Roermund

2011

Architectures and Synthesizers for Ultra-Low Power Fast Frequency-Hopping WSN Radios

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CMOS Analog Design Using All-Region MOSFET Modeling

Schneider

Galup-Montoro

2010

123

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Covering the essentials of analog circuit design, this book takes a unique design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model. Opening chapters focus on device modeling, integrated circuit technology, and layout, whilst later chapters go on to cover noise and mismatch, and analysis and design of the basic building blocks of analog circuits, such as current mirrors, voltage references, voltage amplifiers, and operational amplifiers. An introduction to continuous-time filters is also provided, as are the basic principles of sampled-data circuits, especially switched-capacitor circuits. The final chapter then reviews MOSFET models and describes techniques to extract design parameters. With numerous design examples and exercises also included, this is ideal for students taking analog CMOS design courses and also for circuit designers who need to shorten the design cycle.

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Sizing of MOS transistors for amplifier design

Cited by 8 publications

References 3 publications

Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

FHSS Systems: State-of-the-Art and Power Trade-offs

CMOS Analog Design Using All-Region MOSFET Modeling

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