Single-Port SRAM Cell with Reduced Voltage Supply in Writing Operation

Shiau, Ming-Chuen; Yu, Cheng‐Chieh; Chen, Kuan-Ting

doi:10.1007/978-3-319-04573-3_118

Cited by 4 publications

(4 citation statements)

References 5 publications

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“…In order to resolve write '1' issue of 5T SRAM cells, several techniques have been developed. For example, boosting word line gate voltage [18][19][20][21], reducing the supply voltage V DD [4], [15], [22][23][24][25][26], sizing cell transistors [15], [27][28], reduced bit line voltage [29][30], and raising the source voltage V SS [31][32][33][34]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process [14].…”

Section: Conventional 5t Sram Cellmentioning

confidence: 99%

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Yu¹,

Shiau²,

Tsai³

2018

VLSICS

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In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage V DD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.

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Section: Conventional 5t Sram Cellmentioning

confidence: 99%

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Yu¹,

Shiau²,

Tsai³

2018

VLSICS

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“…Some of these techniques rely on boosted word line voltage [10]- [12], reducing the supply voltage VDD [8]- [9], [13]- [14], sizing cell transistors [15]- [17], reduced bit line voltage [18]- [19], and raising the source voltage V SS [20]- [22]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Yu¹,

Shiau²

2017

IJIEE

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Abstract-In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, as such the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage VDD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby. In particular, the paper introduce a two-phase reading mechanism to improve the reading speed, and thus to avoid unnecessary power consumption. Furthermore, by using the voltage level conversion circuit to pull the voltage of the signal WLC in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to reduce the half-selected cells disturbance.Index Terms-Read/write assist circuitry, standby start-up circuit, static random access memory, voltage level conversion circuit, voltage control circuit.

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“…In order to resolve write '1' issue of 5T SRAM cells, several techniques have been developed. Some of these techniques rely on boosted word line gate voltage [15][16][17][18], reducing the supply voltage V DD [13][14], [19][20][21][22][23], sizing cell transistors [14], [24][25], reduced bitline voltage [26][27], and raising the source voltage V SS [28][29][30][31]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Traditional 5t Sram Cellmentioning

confidence: 99%

Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby

Yu¹,

Shiau²

2016

VLSICS

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In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

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Single-Port SRAM Cell with Reduced Voltage Supply in Writing Operation

Cited by 4 publications

References 5 publications

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby

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