Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.
DOI: 10.1109/isca.2004.1310764
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Single-ISA heterogeneous multi-core architectures for multithreaded workload performance

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Cited by 287 publications
(275 citation statements)
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References 18 publications
(3 reference statements)
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“…Heterogeneous multi-core proposals [18,19] move threads between cores to exploit power-performance-area trade-offs. Those proposals use frequent sampling, via heavy thread migration, to discover good mappings of threads to cores.…”
Section: Introductionmentioning
confidence: 99%
“…Heterogeneous multi-core proposals [18,19] move threads between cores to exploit power-performance-area trade-offs. Those proposals use frequent sampling, via heavy thread migration, to discover good mappings of threads to cores.…”
Section: Introductionmentioning
confidence: 99%
“…Kumar et al [16,17] proposed sampling-based scheduling. DeVuyst et al [9] studied sampling and electron policies adapting to thread execution phases.…”
Section: Related Workmentioning
confidence: 99%
“…There has been a growing tendency toward use of multicore processors in embedded systems since they usually offer higher performance within a specific power budget and thermal envelope compared to single core processors. Heterogeneous multi-processor System-on-Chips (MPSoC) which integrate cores of various types on the same die offer even better performance and power than their homogeneous counterparts as their heterogeneous nature enables them to customize their performance and power characteristics to match the workload requirements [1] [2]. Such heterogeneous MPSoCs are used in a wide range of applications from cell phones (Qualcomms Snapdragon platform) to wireless base stations (Mindspeeds Transcede 4000 processors for 4G wireless base stations).…”
Section: Introductionmentioning
confidence: 99%