Fast thread migration via cache working set prediction

Brown, Jeffery A.; Porter, Leo; Tullsen, Dean M.

doi:10.1109/hpca.2011.5749728

Cited by 33 publications

(9 citation statements)

References 43 publications

(43 reference statements)

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“…The reason is that, the longer the schedule-tick is, the smaller number of reconfigurations happens (reducing hard-costs), and the soft-costs (of recreating BP/ L1 cache states) is more likely to be amortized. The work in [26] gives the similar concludes.…”

Section: Performance Affected By Reconfigurationsupporting

confidence: 67%

CRQ-based fair scheduling on composable multicore architectures

Sun

Wang

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

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As different workloads require different processor resources for better execution efficiency, recent work has proposed composable chip multiprocessors (CCMPs), which provide the capability to configure different number and types of processing cores at system runtime. However, such composable architecture poses a new significant challenge to system scheduler, that is, how to ensure priority-based performance for each task (i.e. fairness), while exploiting the benefits of composability by dynamically changing the hardware configurations to match the parallelism requirements in running tasks (i.e. resource allocation). Current multicore schedulers fail to address this problem, as they traditionally assume fixed number and types of cores.In this work, we introduce centralized run queue (CRQ) and propose an efficiency-based algorithm to address the fair scheduling problem on CCMP. Firstly, instead of using distributed percore run queues, this paper employs CRQ to simplify the scheduling and resource allocation decisions on CCMP, and proposes a pipeline-like scheduling mechanism to hide the large scheduling decision overhead on the centralized queue. Secondly, an efficiency-based dynamic priority (EDP) algorithm is proposed to keep fair scheduling on CCMP, which can not only provide homogenous tasks with performance proportional to their priorities, but also ensure equal-priority heterogeneous tasks to get equivalent performance slowdowns when running simultaneously. To evaluate our design, experimental studies are carried out to compare EDP on CCMP with several state-of-art fair schedulers on symmetric and asymmetric CMPs. Our simulation results demonstrate that, while providing good fairness, EDP on CCMP outperforms the best performing fair scheduler on fixed symmetric and asymmetric CMPs by as much as 11.8% in user-oriented performance, and by 12.5% in system throughput.

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Section: Performance Affected By Reconfigurationsupporting

confidence: 67%

CRQ-based fair scheduling on composable multicore architectures

Sun

Wang

et al. 2012

Proceedings of the 26th ACM International Conference on Supercomputing

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“…A recent paper by Brown et al [13] is the most closely related to this work. They propose specialized hardware in each core to capture and summarize a thread's working set, and the summary is used to prefetch data into the destination CPU's local cache hierarchy.…”

Section: Background and Related Workmentioning

confidence: 77%

Reducing Migration-induced Cache Misses

Reza

Byrd

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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In a large multiprocessor server platform, using multicore chips, the scheduler often migrates a scheduling entity, i.e. a thread or process or virtual machine, in order to achieve better load balancing or ensure fairness. The migration impact is likely to be more severe in virtualized environments, where high over-subscription of logical CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment. We demonstrate the performance benefit of saving and restoring cached data during migration. In particular, we measure the efficiency (benefit per cache block) of saving various subsets of the cached data, in order to balance implementation cost and complexity with improvements in cycle time. We also describe an implementation that moves cached data when a thread migrates, and we show the benefits in terms of reduced misses and reduced processor cycles.

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“…Brown et al investigate cache working set prediction as an enabler for mechanisms that may need frequent migration, for example in systems exploiting loop or tasklevel parallelism, as well as speculative multithreading and helper threading [5]. The time intervals explored in their work are significantly shorter (1 instruction to 1M instructions) than those explored in our work, which affects the predictability of the working set over that interval.…”

Section: Related Workmentioning

confidence: 85%

Cache restoration for highly partitioned virtualized systems

Daly

Cain

2012

IEEE International Symposium on High-Performance Comp Architecture

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The economics of server consolidation have led to the support of virtualization features in almost all server-class systems, with the related feature set being a subject of significant competition. While most systems allow for partitioning at the relatively coarse grain of a single core, some systems also support multiprogrammed virtualization, whereby a system can be more finely partitioned through time-sharing, down to a percentage of a core being allotted to a virtual machine. When multiple virtual machines share a single core however, performance can suffer due to the displacement of microarchitectural state.We introduce cache restoration, a hardware-based prefetching mechanism initiated by the underlying virtualization software when a virtual machine is being scheduled on a core, prefetching its working set and warming its initial environment. Through cycle-accurate simulation of a POWER7 system, we show that when applied to its private per-core L3 last-level cache, the warm cache translates into 20% on average performance improvement for a mixture of workloads on a highly partitioned core, compared to a virtualized server without cache restoration.

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Fast thread migration via cache working set prediction

Abstract: The

Cited by 33 publications

References 43 publications

CRQ-based fair scheduling on composable multicore architectures

CRQ-based fair scheduling on composable multicore architectures

Reducing Migration-induced Cache Misses

Cache restoration for highly partitioned virtualized systems

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